library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.arith;

entity CPU is
	port(clk,rst   : in std_logic;
	     instr		: in
		  dataIn		:in std_logic_vector(15 downto 0);
		  dataOut	:out std_logic_vector(15 downto 0);
		  addr		:out std_logic_vector(15 downto 0)

		  );

end CPU;

architecture behavior of CPU is

begin