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  1. diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
  2. index d623316..14b86b7 100644
  3. --- a/src/mesa/drivers/dri/i965/brw_fs.h
  4. +++ b/src/mesa/drivers/dri/i965/brw_fs.h
  5. @@ -534,11 +534,6 @@ public:
  6.  
  7.     void emit_color_write(int target, int index, int first_color_mrf);
  8.     void emit_fb_writes();
  9. -   bool try_rewrite_rhs_to_dst(ir_assignment *ir,
  10. -                  fs_reg dst,
  11. -                  fs_reg src,
  12. -                  fs_inst *pre_rhs_inst,
  13. -                  fs_inst *last_rhs_inst);
  14.     void emit_assignment_writes(fs_reg &l, fs_reg &r,
  15.                    const glsl_type *type, bool predicated);
  16.     void resolve_ud_negate(fs_reg *reg);
  17. diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
  18. index 9f8a44a..e316606 100644
  19. --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
  20. +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
  21. @@ -528,42 +528,6 @@ fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r,
  22.     }
  23.  }
  24.  
  25. -/* If the RHS processing resulted in an instruction generating a
  26. - * temporary value, and it would be easy to rewrite the instruction to
  27. - * generate its result right into the LHS instead, do so.  This ends
  28. - * up reliably removing instructions where it can be tricky to do so
  29. - * later without real UD chain information.
  30. - */
  31. -bool
  32. -fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir,
  33. -                                   fs_reg dst,
  34. -                                   fs_reg src,
  35. -                                   fs_inst *pre_rhs_inst,
  36. -                                   fs_inst *last_rhs_inst)
  37. -{
  38. -   if (pre_rhs_inst == last_rhs_inst)
  39. -      return false; /* No instructions generated to work with. */
  40. -
  41. -   /* Only attempt if we're doing a direct assignment. */
  42. -   if (ir->condition ||
  43. -       !(ir->lhs->type->is_scalar() ||
  44. -        (ir->lhs->type->is_vector() &&
  45. -         ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1)))
  46. -      return false;
  47. -
  48. -   /* Make sure the last instruction generated our source reg. */
  49. -   if (last_rhs_inst->predicated ||
  50. -       last_rhs_inst->force_uncompressed ||
  51. -       last_rhs_inst->force_sechalf ||
  52. -       !src.equals(&last_rhs_inst->dst))
  53. -      return false;
  54. -
  55. -   /* Success!  Rewrite the instruction. */
  56. -   last_rhs_inst->dst = dst;
  57. -
  58. -   return true;
  59. -}
  60. -
  61.  void
  62.  fs_visitor::visit(ir_assignment *ir)
  63.  {
  64. @@ -574,19 +538,12 @@ fs_visitor::visit(ir_assignment *ir)
  65.     ir->lhs->accept(this);
  66.     l = this->result;
  67.  
  68. -   fs_inst *pre_rhs_inst = (fs_inst *) this->instructions.get_tail();
  69. -
  70.     ir->rhs->accept(this);
  71.     r = this->result;
  72.  
  73. -   fs_inst *last_rhs_inst = (fs_inst *) this->instructions.get_tail();
  74. -
  75.     assert(l.file != BAD_FILE);
  76.     assert(r.file != BAD_FILE);
  77.  
  78. -   if (try_rewrite_rhs_to_dst(ir, l, r, pre_rhs_inst, last_rhs_inst))
  79. -      return;
  80. -
  81.     if (ir->condition) {
  82.        emit_bool_to_cond_code(ir->condition);
  83.     }
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