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- LIBRARY ieee ;
- USE ieee.std_logic_1164.all ;
- USE ieee.std_logic_unsigned.all ;
- ENTITY comp IS
- GENERIC ( N : INTEGER := 8 ) ;
- PORT (A: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
- enable : in STD_LOGIC;
- Igual : OUT STD_LOGIC ) ;
- END comp ;
- ARCHITECTURE comp_be OF comp IS
- BEGIN
- process(enable)
- begin
- if(enable='1' and A="11") then
- Igual <= '1' ;
- else
- Igual <= '0';
- end if;
- end process;
- END comp_be ;
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