Advertisement
Guest User

Untitled

a guest
Nov 28th, 2014
134
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 0.42 KB | None | 0 0
  1. LIBRARY ieee ;
  2. USE ieee.std_logic_1164.all ;
  3. USE ieee.std_logic_unsigned.all ;
  4.  
  5. ENTITY comp IS
  6. GENERIC ( N : INTEGER := 8 ) ;
  7. PORT (A: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
  8. enable : in STD_LOGIC;
  9. Igual : OUT STD_LOGIC ) ;
  10. END comp ;
  11.  
  12. ARCHITECTURE comp_be OF comp IS
  13. BEGIN
  14. process(enable)
  15. begin
  16. if(enable='1' and A="11") then
  17. Igual <= '1' ;
  18. else
  19. Igual <= '0';
  20. end if;
  21. end process;
  22. END comp_be ;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement