library ieee;
use ieee.std_logic_1164.all;

entity lab21 is
port(
    sclr, clr, clk : in std_logic; --zerowanie synchroniczne, asynchroniczne i zegar
    a, b : in std_logic;
    Y : out std_logic;
    W, ST : out std_logic_vector(2 downto 0)
);
end entity;

architecture lab of lab21 is
    --signal st_r, st_n, : std_logic_vector(2 downto 0);
    --zakodowanie stanow automatu
    --constant s1 : std_logic_vector(2 downto 0) := "000";
    --constant s2 : std_logic_vector(2 downto 0) := "001";
    --constant s3 : std_logic_vector(2 downto 0) := "010";
    --constant s4 : std_logic_vector(2 downto 0) := "011";
    --constant s5 : std_logic_vector(2 downto 0) := "100";
    --constant s6 : std_logic_vector(2 downto 0) := "101";
    --constant s7 : std_logic_vector(2 downto 0) := "110";
    --kod stanu don`t care
    --constant sn : std_logic_vector(2 downto 0) := "---";
    --signal xwe : std_logic_vector(1 downto 0);
    --typy wyliczeniowe
    type st_t is (s1, s2, s3, s4, s5, s6, s7);
    signal st_r, st_n, STx : st_t;
    constant sn : st_t := s1;
    attribute syn_encoding : string;
    attribute syn_encoding of st_t : type is "000 001 010 011 100 101 110";
    signal xwe : std_logic_vector(1 downto 0);
    signal Wx : std_logic_vector(2 downto 0);

begin
    --aktualny stan automatu
    p1i:
        process(clr, clk)
        begin
            if(clr = '0') then
                st_r <= s1;
            elsif(rising_edge(clk)) then
                st_r <= st_n;
            end if;
        end process p1i;

    --segment opisujacy tablice przejsc i wyjsc
    xwe <= a&b;
    p2i:
        process(st_r, xwe)
        begin
            case st_r is
                when s1 =>
                    Y <= '0';
                    STx <= s1;
                    case xwe is
                        when "10" => st_n <= s2;  Wx <= "000";
                        when "11" => st_n <= s5; Wx <= "000";
                        when others => st_n <= sn; Wx <= "000";
                    end case;
                when s2 =>
                    Y <= '0';
                    STx <= s2;
                    case xwe is
                        when ("00" or "10") => st_n <= s3; Wx <= "000";
                        when others => st_n <= s5; Wx <= "000";
                    end case;
                when s3 =>
                    Y <= '0';
                    STx <= s3;
                    case xwe is
                        when ("00" or "10") => st_n <= s3; Wx <= "000";
                        when others => st_n <= s4; Wx <= "100";
                    end case;
                when s4 =>
                    Y <= '1';
                    STx <= s4;
                    case xwe is
                        when ("00" or "01") => st_n <= s1; Wx <= "000";
                        when "10" => st_n <= s2; Wx <= "000";
                        when others => st_n <= sn; Wx <= "000";
                    end case;
                when s5 =>
                    Y <= '0';
                    STx <= s5;
                    case xwe is
                        when ("01" or "11") => st_n <= s6; Wx <= "000";
                        when others => st_n <= s7; Wx <= "000";
                    end case;
                when s6 =>
                    Y <= '0';
                    STx <= s6;
                    case xwe is
                        when ("00" or "10") => st_n <= s4; Wx <= "010";
                        when others => st_n <= s6; Wx <= "000";
                    end case;
                when s7 =>
                    Y <= '0';
                    STx <= s7;
                    case xwe is
                        when ("01" or "11") => st_n <= s5; Wx <= "000";
                        when others => st_n <= s4; Wx <= "001";
                    end case;
            end case;
            W <= Wx;
            ST <= STx;
        end process;
end lab;