import os

from migen import *
from misoc.interconnect import wishbone

class UART16550(Module):
    def __init__(self, platform):

        self.slave = slave = wishbone.Interface()


        #UART signal
        self.tx = Signal()
        self.rx = Signal()

        #Modem Signal
        self.rts = Signal()
        self.cts = Signal()
        self.dtr = Signal()
        self.dsr = Signal()
        self.ri = Signal()
        self.dcd = Signal()

        #int
        self.intr = Signal()
        adr_i = Signal(32)

        self.specials += Instance("uart_top",
                                  i_wb_clk_i=ClockSignal(),
                                  i_wb_rst_i=ResetSignal(),

                                  # WISHBONE slave
                                  i_wb_dat_i=slave.dat_r,
                                  o_wb_dat_o=slave.dat_w,
                                  i_wb_adr_i=slave.adr,
                                  i_wb_sel_i=slave.sel,
                                  i_wb_we_i=slave.we,
                                  i_wb_cyc_i=slave.cyc,
                                  i_wb_stb_i=slave.stb,
                                  o_wb_ack_o=slave.ack,

                                  # UART Signal
                                  o_stx_pad_o = self.tx,
                                  i_srx_pad_i = self.rx,

                                  #modem signal
                                  o_rts_pad_o = self.rts,
                                  i_cts_pad_i = self.cts,
                                  o_dtr_pad_o = self.dtr,
                                  i_dsr_pad_i = self.dsr,
                                  i_ri_pad_i = self.ri,
                                  i_dcd_pad_i = self.dcd,

                                  #interrupt
                                  o_int_o=self.intr
        )

        #self.comb += adr_i[2:].eq(slave.adr)


        sdcard_path = os.path.abspath(os.path.dirname(__file__))
        platform.add_source_dir(os.path.join(sdcard_path, "verilog"))