library ieee;
use ieee.std_logic_1164.all;

package FSM_codes is
  -- define state assignment - binary

  constant SWIDTH: integer := 3;
  subtype state_type is
    std_logic_vector( SWIDTH-1 downto 0 );

  constant	LOAD_IR:	state_type := "0000";
  constant	UPDATE_PC:	state_type := "0001";
  constant	DECODE_RN:	state_type := "0010";
  constant	READ_RM:	state_type := "0100";
  constant ALU_ST: state_type := "1000";
  constant WRITE_RDRN: state_type := "0011"

end package;

----------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.datapath_declarations.all;
use work.ff.all;
use work.FSM_codes.all;

entity FSM is

  port ( clk :    in std_logic;
        reset :   in std_logic;
        opcode :  in std_logic_vector( 2 downto 0 );
        op :      in std_logic_vector( 1 downto 0 );
        loadir :  out std_logic;
        loadpc :  out std_logic;
        nsel :    out std_logic_vector(1 downto 0);
        write :   out std_logic;
        vsel :    out std_logic_vector( 1 downto 0 );
        loada :   out std_logic;
        loadb :   out std_logic;
        asel  :   out std_logic;
        bsel  :   out std_logic;
        loadc :   out std_logic;
        loads :   out std_logic;
        msel  :   out std_logic;
        mwrite :  out std_logic
        );
end FSM;

architecture impl of FSM is
  signal	current_state, next_state, next1:	std_logic_vector(SWIDTH-1	downto	0);
begin

  asel <= '0';
  bsel <= '0';
  msel <= '0';
  mwrite <= '0';

  loadir <= '1' when current_state = LOAD_IR else '0';
  loadpc <= '1' when current_state = UPDATE_PC else '0';
  loada <= '1' when current_state = DECODE_RN else '0';
  loadb <= '1' when current_state = READ_RM else '0';
  loads <= '1' when current_state = ALU_ST else '0';
  write <= '1' when current_state = WRITE_RDRN else '0';
  loadc <= '1' when current_state = WRITE_RDRN else '0';





  state_reg: vDFF generic map(SWIDTH) port map(clk, next_state, current_state);

  -- next state logic (e.g.)
  process(all) begin
    case? opCode & op & current_state is
     when "---" & "--" & LOAD_IR => next1 <= UPDATE_PC;
     when "---" & "--" & UPDATE_PC => next1 <= DECODE_RN;
     when "101" & "--" & DECODE_RN => next1 <= READ_RM;
     when "110" & "10" & DECODE_RN => next1 <= WRITE_RDRN;
     when "---" & "--" & READ_RM => next1 <= ALU_ST;
     when "101" & "01" & ALU_ST => next1 <= LOAD_IR;
     when "101" & "00" & ALU_ST => next1 <= WRITE_RDRN;
     when "101" & "1-" & ALU_ST => next1 <= WRITE_RDRN;
     when "---" & "--" & WRITE_RDRN => next1 <= LOAD_IR;


    end case?;
  end process;




  next_state <= LOAD_IR when reset else next1;
end impl;

----------------------------------------------------------------------
----------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.datapath_declarations.all;
use work.ff.all;

entity CPUentity is

--  datapath_insta : datapath generic map(16, 8) port map( );
--  FSM_insta: FSM generic map( ) port map( );
end CPUentity;

architecture impl of CPUentity is
begin
end impl;