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  1. library ieee;
  2.     use ieee.std_logic_1164.ALL;
  3.     use ieee.numeric_std.ALL;
  4.  
  5. entity DualOperationRAM is
  6.     generic (
  7.         ram_addressWidth        : positive := 13;
  8.         ram_dataWidth           : positive := 32;
  9.         ram_byteenableWidth : positive := 4
  10.     );
  11.    
  12.     port (
  13.         ram_doubleClk       : in std_logic;
  14.    
  15.         ram_address         : out std_logic_vector( (ram_addressWidth-1) downto 0);              
  16.         ram_chipselect    : out std_logic;                      
  17.         ram_write         : out std_logic;                
  18.         ram_readdata      : in std_logic_vector( (ram_dataWidth-1) downto 0);                    
  19.         ram_writedata     : out std_logic_vector( (ram_dataWidth-1) downto 0);                        
  20.         ram_byteenable    : out std_logic_vector( (ram_byteenableWidth-1) downto 0);
  21.         ram_clken         : out std_logic;            
  22.  
  23.         dualOperationRam_writeClk       : in std_logic;        
  24.         dualOperationRam_write          : in std_logic;            
  25.         dualOperationRam_writeAddress     : in std_logic_vector( (ram_addressWidth-1) downto 0);                
  26.         dualOperationRam_writedata      : in std_logic_vector( (ram_dataWidth-1) downto 0);                        
  27.         dualOperationRam_writebyteenable: in std_logic_vector( (ram_byteenableWidth-1) downto 0);  
  28.        
  29.         dualOperationRam_readClk        : in std_logic;
  30.         dualOperationRam_read           : in std_logic;            
  31.         dualOperationRam_readAddress      : in std_logic_vector( (ram_addressWidth-1) downto 0);                
  32.         dualOperationRam_readdata       : out std_logic_vector( (ram_dataWidth-1) downto 0);                        
  33.         dualOperationRam_readbyteenable : in std_logic_vector( (ram_byteenableWidth-1) downto 0)  
  34.     );
  35. end entity;
  36.  
  37.  
  38. architecture Test of DualOperationRAM is
  39.     constant writeOperation : std_logic := '0';
  40.     constant readOperation : std_logic := '1';
  41.  
  42.     signal operation : std_logic := writeOperation;
  43.     signal readRequest : std_logic := '0';
  44.     signal writeRequest : std_logic := '0';
  45.    
  46.     signal writeMask : std_logic := '0';
  47.     signal readMask : std_logic := '0';
  48.        
  49.     signal read_q : std_logic_vector( (ram_dataWidth-1) downto 0) := (others => '0');  
  50. begin
  51.     -- Write/Read switch (na zmianę read/write)
  52.     process(ram_doubleClk)
  53.     begin
  54.         if (rising_edge(ram_doubleClk)) then
  55.             if (operation = readOperation) then
  56.                 operation <= writeOperation;
  57.             else
  58.                 operation <= readOperation;
  59.             end if;
  60.         end if;
  61.     end process;
  62.  
  63.    
  64.    
  65.     -- Holding write request until write cycle
  66.     process(ram_doubleClk)
  67.     begin
  68.         if (rising_edge(ram_doubleClk)) then
  69.        
  70.             -- Kiedy wystawiono chęć zapisana, kiedy zegar zapisywania jest w stanie wysokim
  71.             -- (aby uniknąc ponownego żądania zapisania, pojawiała się taka sytuacja bez drugiego warunku,
  72.             -- bo maska "writeMask" jest zerowana gdy stan zegara przejdzie na 0)
  73.             -- oraz kiedy maska jest równa 0 - aby nie wykonało dwóch żądań zapisu
  74.             if (dualOperationRam_write = '1' and dualOperationRam_writeClk = '1' and writeMask = '0') then
  75.                 writeRequest <= '1';
  76.                 writeMask <= '1';
  77.             elsif (operation = writeOperation) then
  78.                 writeRequest <= '0';
  79.             end if;
  80.            
  81.             if (dualOperationRam_writeClk = '0' and writeRequest = '0') then
  82.                 writeMask <= '0';
  83.             end if;
  84.         end if;
  85.     end process;
  86.    
  87.    
  88.    
  89.    
  90.     -- Holding read request until read cycle
  91.     process(ram_doubleClk)
  92.     begin
  93.         if (rising_edge(ram_doubleClk)) then
  94.             -- Analogicznie jak przy zapisie
  95.             if (dualOperationRam_read = '1' and dualOperationRam_readClk = '1' and readMask = '0') then
  96.                 readRequest <= '1';
  97.                 readMask <= '1';
  98.             elsif (operation = readOperation) then
  99.                 readRequest <= '0';
  100.             end if;
  101.            
  102.             if (dualOperationRam_readClk = '0' and readRequest = '0') then
  103.                 readMask <= '0';
  104.             end if;
  105.         end if;
  106.     end process;
  107.    
  108.    
  109.    
  110.     -- Read data output
  111.     process(dualOperationRam_readClk)
  112.     begin
  113.         if (rising_edge(dualOperationRam_readClk)) then
  114.             dualOperationRam_readdata <= read_q;
  115.         end if;
  116.     end process;
  117.    
  118.    
  119.    
  120.     -- Transfering data to RAM
  121.     process(ram_doubleClk)
  122.         variable readPerformed : std_logic := '0';
  123.         variable read_q_prepare : std_logic := '0';
  124.     begin
  125.         if (rising_edge(ram_doubleClk)) then
  126.             if (readRequest = '1' and operation = readOperation) then
  127.                 ram_chipselect <= '1';
  128.                 ram_clken <= '1';
  129.                 ram_write <= '0';      
  130.                
  131.                 ram_address <= dualOperationRam_readAddress;
  132.                 ram_writedata <= (others => '0');
  133.                 ram_byteenable <= dualOperationRam_readbyteenable;
  134.                
  135.                 readPerformed := '1';
  136.             elsif (writeRequest= '1' and operation = writeOperation) then
  137.            
  138.                 ram_chipselect <= '1';
  139.                 ram_write <= '1';
  140.                 ram_clken <= '1';
  141.                
  142.                 ram_address <= dualOperationRam_writeAddress;
  143.                 ram_writedata <= dualOperationRam_writedata;
  144.                 ram_byteenable <= dualOperationRam_writebyteenable;
  145.                
  146.             else
  147.                 ram_address <= (others => '0');
  148.                 ram_writedata <= (others => '0');
  149.                 ram_byteenable <= (others => '0');
  150.                 ram_chipselect <= '0';
  151.                 ram_write <= '0';
  152.                 ram_clken <= '0';
  153.             end if;
  154.            
  155.             -- Jeżeli w cyklu odczytywania wpiszemy adres i resztę danych, to zostaną one ustawione przez układ sekwencyjny dopiero w następnym takcie zegara
  156.             -- Dlatego zapisujemy informację o tym że takie działanie zostało zapisane
  157.             if (operation = writeOperation and readPerformed = '1') then
  158.                 read_q_prepare := '1';
  159.             end if;
  160.            
  161.            
  162.             -- ...i gdy miną dwa cykle - czyli znowu będzie odczytywanie (no i był sygnał że czekamy na danę)
  163.             -- to wtedy na wyjściu portu ram będą dane do oczytu, które zapisujemy do sygnału read_q
  164.             -- którego zawartość będzie wystawiona według taktowania zegara odczytującego
  165.             if (operation = readOperation and readPerformed = '1' and read_q_prepare = '1') then
  166.                 read_q <= ram_readdata;
  167.                 readPerformed := '0';
  168.                 read_q_prepare := '0';
  169.             end if;
  170.         end if;
  171.     end process;   
  172. end architecture;
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