VLSI_L3

//L3_Ex1
module ex1(out,A,B,SEL);
    input A,B,SEL;
    output out;
    wire w1,w2,w3;
    not gate_NU(w1,SEL);
    and gate1_SI(w2,w1,A);
    and gate2_SI(w3,SEL,B);
    or gate_SAU(out,w2,w3);
endmodule

module test_ex1();
    reg A,B,SEL;
    wire out;
    initial begin
        A=0;B=0;SEL=0;
        #50 B=1;
        #50 A=1;B=0;SEL=1;
        #50 B=1;
    #50 B=1;
    end
    ex1 test1(out,A,B,SEL);
endmodule
//L2_Ex1_B
module ex1_B(out,A,B,SEL);
    input A,B,SEL;
    output out;
    //assign out = (~SEL&A)|(SEL&B);
    //op conditional cond ? exp1:exp2;
    assign out = SEL? B : A;
endmodule
module test_ex1_B();
    reg A,B,SEL;
    wire out;
    initial begin
        A=0;B=0;SEL=0;
        #50 B=1;
        #50 A=1;B=0;SEL=1;
        #50 B=1;
    #50 SEL=0;
    end
    ex1_B test1(out,A,B,SEL);
endmodule



//---------

module test_ex2();
    reg A,B,Cin;
    wire out,cout;
    initial begin
        A=0;B=0;Cin=0;
        #50 B=1;
        #50 A=1;
        #50 Cin=1;
    #50 A=1;
    end
    sum1b test1(cout,out,A,B,Cin);
endmodule
//sum4bit
module ex2_B(Cout,S,A,B,Cin);
    input [3:0]A,B;
    input Cin;
    output Cout;
    output [3:0]S;
    wire w1,w2,w3;
    sum1b s1(w1,S[0],A[0],B[0],Cin);
    sum1b s2(w2,S[1],A[1],B[1],Cin);
    sum1b s3(w3,S[2],A[2],B[2],Cin);
    sum1b s4(Cout,S[3],A[3],B[3],Cin);
endmodule
module sum1b(Cout,out,A,B,Cin);
    input A,B,Cin;
    output Cout,out;
    assign {Cout,out} = A+B+Cin;
endmodule
module test_ex2_B();
    reg [3:0]A,B;
    reg Cin;
    wire [3:0]out;
    wire cout;
    initial begin
        A=10;B=6;Cin=0;
        #50 B=1;
        #50 A=1;
        #50 Cin=1;
    #50 A=1;
    end
    ex2_B test2b(cout,out,A,B,Cin);
endmodule