comp

entity comp_egalitate_1_bit is
    port(A,B: in BIT;
    Y: out BIT);
end comp_egalitate_1_bit;

architecture arh of comp_egalitate_1_bit is

component poarta_xnor
    port(A,B: in BIT;
    C: out BIT);
end component poarta_xnor;

begin
    C1: poarta_xnor port map(A,B,Y);
end arh;