`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/07/2017 10:11:08 AM
// Design Name:
// Module Name: i2s_inf
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module i2s_inf(
input sys_clk, //sys_clk = 98.304 Mhz
input rst,
input bclk,
input lrclk,
input adc_in, // codec adc_sdata kimenete
//input [23:0] dac_sdata, //modul 24 bit-es bemenete
output [23:0] adc_sdata , //modul 24 bit-es kimenete
output left_valid,
output right_valid,
output mclk
);

reg [9:0] clk_div = 0;
reg [1:0] bclk_shr;
reg [1:0] lrclk_shr;
reg [4:0] bcnt = 0;
(* mark_debug = "true" *) (* dont_touch = "true" *) reg [23:0] adc_shr=0; //adc shiftregiszter
(* mark_debug = "true" *) (* dont_touch = "true" *) reg reg_left_valid = 0;
(* mark_debug = "true" *) (* dont_touch = "true" *) reg reg_right_valid = 0;

always @ (posedge sys_clk)
if (!rst)
   clk_div <= 0;
else
   clk_div <= clk_div + 1;

assign mclk = clk_div[2]; //el?állítjuk a sys_clk-ból a 49.152 MHz-t az CODEC-nek

//bitcount
assign right_valid = reg_right_valid;
assign left_valid = reg_left_valid;
assign adc_sdata =(reg_right_valid == 1 || reg_left_valid == 1 ? adc_shr: 24'd0);

//bclk = 64*LRCLK = 6.144Mhz, minden 16. sys_clk
//bclk,lrclk mintavételezése
always @ (posedge sys_clk)
begin
    if(!rst)
        begin
              bclk_shr <= 0;
        end
    else
        begin
              bclk_shr <= {bclk_shr[0],bclk};

        end
end

//adc_sdata beshiftelése
always @ (posedge sys_clk)
begin
    if(!rst)
         begin
              bcnt <= 5'd0;
         end
    else
         begin
              if (bclk_shr == 2'b01) //bclk felfutó él
                  begin
                        adc_shr <= {adc_shr[22:0], adc_in};
                        bcnt <= bcnt + 1;
                  end
              else if (bclk_shr == 2'b10) //bclk lefutó él
                  begin
                        lrclk_shr <= {lrclk_shr[0],lrclk};
                  end
         end
end

always @ (posedge sys_clk)
begin
    if (!rst)
        begin
            reg_left_valid <= 0;
            reg_right_valid <= 0;
        end
    else
        begin
            if (bcnt==31 & lrclk_shr == 2'b01)
                reg_left_valid <= 1;
            else
                reg_left_valid <= 0;

            if (bcnt==31 & lrclk_shr == 2'b10)
                reg_right_valid <= 1;
            else
                reg_right_valid <= 0;
        end
end

endmodule