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  1. /*
  2.  * Copyright(C) NXP Semiconductors, 2012
  3.  * All rights reserved.
  4.  *
  5.  * Software that is described herein is for illustrative purposes only
  6.  * which provides customers with programming information regarding the
  7.  * LPC products.  This software is supplied "AS IS" without any warranties of
  8.  * any kind, and NXP Semiconductors and its licensor disclaim any and
  9.  * all warranties, express or implied, including all implied warranties of
  10.  * merchantability, fitness for a particular purpose and non-infringement of
  11.  * intellectual property rights.  NXP Semiconductors assumes no responsibility
  12.  * or liability for the use of the software, conveys no license or rights under any
  13.  * patent, copyright, mask work right, or any other intellectual property rights in
  14.  * or to any products. NXP Semiconductors reserves the right to make changes
  15.  * in the software without notification. NXP Semiconductors also makes no
  16.  * representation or warranty that such application will be suitable for the
  17.  * specified use without further testing or modification.
  18.  *
  19.  * Permission to use, copy, modify, and distribute this software and its
  20.  * documentation is hereby granted, under NXP Semiconductors' and its
  21.  * licensor's relevant copyrights in the software, without fee, provided that it
  22.  * is used in conjunction with NXP Semiconductors microcontrollers.  This
  23.  * copyright, permission, and disclaimer notice must appear in all copies of
  24.  * this code.
  25.  */
  26.  
  27. #include "board.h"
  28.  
  29. /* The System initialization code is called prior to the application and
  30.    initializes the board for run-time operation. */
  31.  
  32. /*****************************************************************************
  33.  * Private types/enumerations/variables
  34.  ****************************************************************************/
  35.  
  36. /* Structure for initial base clock states */
  37. struct CLK_BASE_STATES {
  38.     CHIP_CGU_BASE_CLK_T clk;    /* Base clock */
  39.     CHIP_CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */
  40.     bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
  41.     bool powerdn;       /* Set to true if the base clock is initially powered down */
  42. };
  43.  
  44. /* Initial base clock states are mostly on */
  45. STATIC const struct CLK_BASE_STATES InitClkStates[] = {
  46.     {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
  47. #if defined(USE_RMII)
  48.     {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
  49. #else
  50.     {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
  51. #endif
  52.     /* Clocks derived from dividers */
  53.     {CLK_BASE_LCD, CLKIN_IDIVC, true, false},
  54.     {CLK_BASE_USB1, CLKIN_IDIVD, true, true}
  55. };
  56.  
  57. /* SPIFI high speed pin mode setup */
  58. STATIC const PINMUX_GRP_T spifipinmuxing[] = {
  59.     {0x3, 3,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},   /* SPIFI CLK */
  60.     {0x3, 4,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},   /* SPIFI D3 */
  61.     {0x3, 5,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},   /* SPIFI D2 */
  62.     {0x3, 6,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},   /* SPIFI D1 */
  63.     {0x3, 7,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},   /* SPIFI D0 */
  64.     {0x3, 8,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)}    /* SPIFI CS/SSEL */
  65. };
  66.  
  67. STATIC const PINMUX_GRP_T pinmuxing[] = {
  68.     /* RMII pin group */
  69. #ifdef explorer_init
  70.     {0x1, 15,
  71.      (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
  72.     {0x0, 0,
  73.      (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)},
  74.     {0x1, 16,
  75.      (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)},
  76.     {0x0, 1,  (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6)},
  77.     {0x1, 19,
  78.      (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)},
  79.     {0x1, 18, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
  80.     {0x1, 20, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
  81.     {0x1, 17,
  82.      (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
  83.     {0x2, 0,  (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)},
  84.     /* Board LEDs */
  85.     {0x2, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLDOWN | SCU_MODE_FUNC0)},
  86.     {0x2, 12, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLDOWN | SCU_MODE_FUNC0)},
  87.     /*  I2S  */
  88.     {0x3, 0,  (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
  89.     {0x6, 0,  (SCU_PINIO_FAST | SCU_MODE_FUNC4)},
  90.     {0x7, 2,  (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
  91.     {0x6, 2,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
  92.     {0x7, 1,  (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
  93.     {0x6, 1,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
  94.  
  95.     /* GENERAL GPIO PINS - ODT */
  96.     {0x1, 15, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)},     /* GPIO0[2] */
  97.     {0x2,  0, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)},     /* GPIO5[0]*/
  98.     {0x2, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)},     /* GPIO1[11]*/
  99.     {0x1,  6, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)},     /* GPIO1[9]*/
  100.     {0x2,  7, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)},     /* GPIO0[7]*/
  101.     {0x2, 10, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)},     /* GPIO0[14]*/
  102.     {0x1,  0, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)},     /* GPIO0[4]*/
  103.     {0x2,  2, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)},     /* GPIO5[2]*/
  104.     {0x2,  5, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)},     /* GPIO5[5]*/
  105.  
  106.     {0x0, 16, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)},     /* GPIO0[3]*/
  107.     {0x2, 13, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)},     /* GPIO1[13]*/
  108.     {0x2, 12, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)},     /* GPIO1[12]*/
  109.     {0x1,  8, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)},     /* GPIO1[1]*/
  110.     {0x6, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)},     /* GPIO3[7]*/
  111.     {0x6,  9, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)},     /* GPIO3[5]*/
  112.     {0x2,  9, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)},     /* GPIO1[10]*/
  113.     {0x0,  1, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)},     /* GPIO0[1]*/
  114.     {0x2,  1, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)},     /* GPIO5[1]*/
  115.  
  116.     {0x1, 13, (SCU_MODE_PULLDOWN | SCU_MODE_FUNC1)},                                        /* P1_13 : UART1_TXD */
  117.     {0x1, 14, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC1)},   /* P1_14 : UART1_RX */
  118. #endif
  119.  
  120.     {0x2, 3, (SCU_MODE_PULLDOWN | SCU_MODE_FUNC1)},                                         /* P2_3 : UART3_TXD */
  121.     {0x2, 4, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC1)},    /* P2_4 : UART3_RX */
  122.  
  123.     /* Board LEDs */
  124.     {0x8, 2, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLDOWN | SCU_MODE_FUNC0)},
  125.     {0x8, 3, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLDOWN | SCU_MODE_FUNC0)},
  126.     {0x8, 4, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLDOWN | SCU_MODE_FUNC0)},
  127.     {0x8, 5, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLDOWN | SCU_MODE_FUNC0)},
  128.     {0x8, 6, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLDOWN | SCU_MODE_FUNC0)},
  129.     {0x8, 7, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLDOWN | SCU_MODE_FUNC0)},
  130.  
  131.  
  132.     //input
  133.     {0xC, 9, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC4)},
  134.  
  135.  
  136.  
  137.     /* External data lines D0 .. D31 */
  138.     {0x1, 7,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  139.     {0x1, 8,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  140.     {0x1, 9,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  141.     {0x1, 10,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  142.     {0x1, 11,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  143.     {0x1, 12,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  144.     {0x1, 13,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  145.     {0x1, 14,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  146.     {0x5, 4,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  147.     {0x5, 5,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  148.     {0x5, 6,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  149.     {0x5, 7,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  150.     {0x5, 0,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  151.     {0x5, 1,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  152.     {0x5, 2,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  153.     {0x5, 3,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  154.     {0xD, 2,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  155.     {0xD, 3,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  156.     {0xD, 4,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  157.     {0xD, 5,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  158.     {0xD, 6,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  159.     {0xD, 7,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  160.     {0xD, 8,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  161.     {0xD, 9,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  162.     {0xE, 5,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  163.     {0xE, 6,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  164.     {0xE, 7,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  165.     {0xE, 8,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  166.     {0xE, 9,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  167.     {0xE, 10,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  168.     {0xE, 11,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  169.     {0xE, 12,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  170.  
  171.     /* Address lines A0 .. A23 */
  172.     {0x2, 9,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  173.     {0x2, 10,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  174.     {0x2, 11,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  175.     {0x2, 12,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  176.     {0x2, 13,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  177.     {0x1, 0,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  178.     {0x1, 1,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  179.     {0x1, 2,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  180.     {0x2, 8,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  181.     {0x2, 7,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  182.     {0x2, 6,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  183.     {0x2, 2,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  184.     {0x2, 1,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  185.     {0x2, 0,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  186.     {0x6, 8,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1)},
  187.     {0x6, 7,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1)},
  188.     {0xD, 16,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  189.     {0xD, 15,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
  190.     {0xE, 0,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  191.     {0xE, 1,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  192.     {0xE, 2,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  193.     {0xE, 3,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  194.     {0xE, 4,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  195.     {0xA, 4,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  196.  
  197.     /* EMC control signals */
  198.     {0x1, 4,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)}, //Byte Lane select signal 0
  199.     {0x6, 6,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1)}, //Byte Lane select signal 1
  200.     {0xD, 13,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},//Byte Lane select signal 2
  201.     {0xD, 10,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},//Byte Lane select signal 3
  202.     {0x6, 9,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)}, //EMC_DYCS0
  203.     {0x1, 6,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
  204.     {0x6, 4,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)}, //EMC_CAS
  205.     {0x6, 5,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)}, //EMC_RAS
  206.     {0x6, 11,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)}, //EMC_CKEOUT0
  207.     {0x6, 12,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)}, //EMC_DQMOUT0
  208.     {0x6, 10,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)}, //EMC_DQMOUT1
  209.     {0xD, 0,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},  //EMC_DQMOUT2
  210.     {0xE, 13,(SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)}, //EMC_DQMOUT3
  211.     {0x1, 3,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, //EMC OE
  212.     {0x1, 4,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, //EMC_BLS0
  213.     {0x6, 6,  (SCU_PINIO_FAST | SCU_MODE_FUNC1)}, //EMC_BLS1
  214.     {0x1, 5,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, //EMC_CS0
  215.     {0x1, 6,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)}  //EMC_WE
  216.  
  217.  
  218.  
  219. };
  220.  
  221.  
  222. /*****************************************************************************
  223.  * Public types/enumerations/variables
  224.  ****************************************************************************/
  225.  
  226. /*****************************************************************************
  227.  * Private functions
  228.  ****************************************************************************/
  229.  
  230. /*****************************************************************************
  231.  * Public functions
  232.  ****************************************************************************/
  233.  
  234.  
  235. /* Sets up system pin muxing */
  236. void Board_SetupMuxing(void)
  237. {
  238.  
  239.     /* Setup system level pin muxing (and External Memory Controller)*/
  240.     Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
  241.  
  242.  
  243.     /* SPIFI pin setup is done prior to setting up system clocking */
  244.     Chip_SCU_SetPinMuxing(spifipinmuxing, sizeof(spifipinmuxing) / sizeof(PINMUX_GRP_T));
  245.  
  246.  
  247. }
  248.  
  249. /* Set up and initialize clocking prior to call to main */
  250. void Board_SetupClocking(void)
  251. {
  252.     unsigned int i;
  253.  
  254.     Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true);
  255.  
  256.     /* Reset and enable 32Khz oscillator */
  257.     LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
  258.     LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
  259.  
  260.  
  261.  
  262.  
  263.  
  264.     /* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
  265.        Divide rate is based on CPU speed and speed of SPI FLASH part. */
  266. #if (MAX_CLOCK_FREQ > 180000000)
  267.     Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
  268. #else
  269.     Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
  270. #endif
  271.     Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
  272.  
  273.     /* Setup system base clocks and initial states. This won't enable and
  274.        disable individual clocks, but sets up the base clock sources for
  275.        each individual peripheral clock. */
  276.     for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
  277.         Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
  278.                                 InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
  279.     }
  280.  
  281.  
  282.  
  283.  
  284. }
  285.  
  286.  
  287. /**EMC*/
  288. /* Keil SDRAM timing and chip Config */
  289. STATIC const IP_EMC_DYN_CONFIG_T AS4C2M32SA_config =
  290. {
  291.     //EMCCLK=102mhz  => 1 clk = 9.8 ns
  292.     EMC_NANOSECOND(80),                 /*!<         Refresh period*/
  293.     0x1,                                /*!<         Clock*/
  294.     EMC_NANOSECOND(18),                 /*!< (tRP)   Precharge Command Period */                          //Datablad: min 18 ns
  295.     EMC_NANOSECOND(42),                 /*!< (tRAS)  Active to Precharge Command Period */               //Datablad: min 42 ns
  296.     EMC_NANOSECOND(70),                 /*!< (tSREX) Self Refresh Exit Time */                          // ?
  297.     EMC_CLOCK(0x01),                    /*!< (tAPR)  Last Data Out to Active Time */                     // ?
  298.     EMC_CLOCK(0x05),                    /*!< (tDAL)  Data In to Active Command Time */                   // tRP + tWR = 18ns + 2 clk
  299.     EMC_NANOSECOND(12),                 /*!< (tWR)   Write Recovery Time */                               //Datablad: min 2 clockcycles no max
  300.     EMC_NANOSECOND(60),                 /*!< (tRC)   Active to Active Command Period */                   //Datablad: min 60 ns
  301.     EMC_NANOSECOND(60),                 /*!< (tRFC)  Auto-refresh Period */                              //Datablad: min 60 ns
  302.     EMC_NANOSECOND(70),                 /*!< (tXSR)  Exit Selt Refresh */                                //Datablad: min 60+1.5 ns
  303.     EMC_NANOSECOND(12),                 /*!< (tRRD)  Active Bank A to Active Bank B Time */              //Datablad: min 12 ns
  304.     EMC_CLOCK(0x02),                    /*!< (tMRD)  Load Mode register command to Active Command */     //Datablad min 2 clockcycles
  305.     {
  306.         {
  307.             EMC_ADDRESS_DYCS0,  /* DYCS0 for SDRAM - BaseAddress 0x28000000*/
  308.             3,  /* RAS */
  309.  
  310.             EMC_DYN_MODE_WBMODE_PROGRAMMED | //Mode Register value
  311.             EMC_DYN_MODE_OPMODE_STANDARD |
  312.             EMC_DYN_MODE_CAS_3 |
  313.             EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
  314.             EMC_DYN_MODE_BURST_LEN_4,
  315.  
  316.             EMC_DYN_CONFIG_DATA_BUS_32 |    //Dynamic Configuration value
  317.             EMC_DYN_CONFIG_LPSDRAM |
  318.             EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS |
  319.             EMC_DYN_CONFIG_MD_SDRAM
  320.         },
  321.         {0, 0, 0, 0},  //DYCS1
  322.         {0, 0, 0, 0},  //DYCS2
  323.         {0, 0, 0, 0}   //DYSC3
  324.     }
  325. };
  326.  
  327. STATIC const IP_EMC_STATIC_CONFIG_T S29GL64N90_config = {
  328.     0,
  329.     EMC_STATIC_CONFIG_MEM_WIDTH_32 |
  330.     EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
  331.     EMC_STATIC_CONFIG_BLS_HIGH /* |
  332.                                   EMC_CONFIG_BUFFER_ENABLE*/,
  333.  
  334.     EMC_NANOSECOND(0),
  335.     EMC_NANOSECOND(65),
  336.     EMC_NANOSECOND(90),
  337.     EMC_NANOSECOND(90),
  338.     EMC_NANOSECOND(35),
  339.     EMC_CLOCK(4)
  340. };
  341.  
  342.  
  343. /* EMC clock delay */
  344. #define CLK0_DELAY 16 //(?)
  345. /* Setup external memories */
  346. void Board_SetupExtMemory(void)
  347. {
  348. //    LPC_EMC->DYNAMICCONFIG0   |= (0 << 19); //disable buffers
  349. //    LPC_EMC->STATICCONFIG0    |= (0 << 19);  //disable buffers
  350. //  /* Setup EMC Delays */
  351. //  /* Move all clock delays together */
  352. //  LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12));
  353. //
  354. //  /* Setup EMC Clock Divider for divide by 2 - this is done in both the CCU (clocking)
  355. //     and CREG. For frequencies over 120MHz, a divider of 2 must be used. For frequencies
  356. //     less than 120MHz, a divider of 1 or 2 is ok. */
  357. //  Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2); // BASE_M4_CLK / 2
  358. //  LPC_CREG->CREG6 |= (1 << 16);
  359. //  /* Enable EMC clock */
  360. //  Chip_Clock_Enable(CLK_MX_EMC);
  361. //  /* Init EMC Controller -Enable-LE mode */
  362. //  Chip_EMC_Init(1, 0, 0);
  363. //  /* Init EMC Dynamic Controller */
  364. //  Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_T *) &AS4C2M32SA_config);
  365. //  /* Init EMC Static Controller CS0 */
  366. //  Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_T *) &S29GL64N90_config);
  367. //
  368. //    //LPC_EMC->DYNAMICCONFIG0 = 0x5300;  // BRC mapping
  369. //    //LPC_EMC->DYNAMICCONFIG0 = 0x4300;  // RBC mapping
  370. //    LPC_EMC->DYNAMICCONFIG0   |= (1 << 19); //enable buffers
  371. //  /* Enable Buffer for External Flash */
  372. //  LPC_EMC->STATICCONFIG0 |= 1 << 19;
  373.  
  374.     uint32_t *pConfig;
  375.     /**Step 1: Enable EMC clocking, select SDRAM type, and select SDRAM slew rates*/
  376.     //Set CREG6 control register for EMC_CLK_SEL (bit # 16) = 1 => EMC_CLK_DIV divided by 2.
  377.     //pConfig=(volatile uint32_t *)0x4004312C;
  378.     //*pConfig |= 1 << 16;                                                                                            //CONFIRMED 0x00000001
  379.  
  380.     //Set CCU1 branch clock configuration register. Clock divider value (bit 5:7) 0x1 (divided by 2)
  381.     pConfig=(volatile uint32_t *)0x40051478;
  382.     //*pConfig |= 0x1 << 5;                                                                                           //UNCONFIRMED BUT ASSUMED
  383.     *pConfig|=0x21;
  384.  
  385.     *pConfig=(1 << 2) | (1 << 1) | 1;
  386.  
  387.     LPC_SCU->EMCDELAYCLK = 0x00005555;
  388.  
  389.    /* Set Address mapping for MT48LC16M16 cascaded as 32-bit memory: */
  390.  
  391.    /* 256Mbit(16Mb x 4 x 4 banks), row len = 13, column len = 10     */
  392.  
  393.    /* bit[14] = 1    bit]11:9] = 100   bit[8:7] = 01                 */
  394.  
  395.  
  396. //   LPC_EMC->DYNAMICCONFIG0    = (1 << 14) |  /* AM[14]   = 1                   */
  397. //
  398. //                                (0 << 12) |  /* AM[12]   = 0                   */
  399. //
  400. //                                (4 <<  9) |  /* AM[11:9] = 4                   */
  401. //
  402. //                                (1 <<  7) ;  /* AM[8:7]  = 1                   */
  403.  
  404.     pConfig=(volatile uint32_t *)0x40005100;    //Dynamic Memory Configuration Register
  405.     *pConfig |= 0x6 << 7;                       //AM0 Address mapping bit 7:12                                       //CONFIRMED 0x00000300
  406.     *pConfig |= 0x1 << 14;                      //AM1 Address mapping bit 14
  407.  
  408.  
  409.    LPC_EMC->DYNAMICRASCAS0    = 0x00000303;  /* Latency: RAS 3, CAS 3 CCLK cyc.*/
  410.  
  411.    LPC_EMC->DYNAMICREADCONFIG = 0x00000001;  /* Command delayed by 1/2 CCLK    */
  412.  
  413.    LPC_EMC->DYNAMICRP    = 4;
  414.  
  415.    LPC_EMC->DYNAMICRAS = 7;
  416.  
  417.    LPC_EMC->DYNAMICSREX = 9;
  418.  
  419.    LPC_EMC->DYNAMICAPR = 1;
  420.  
  421.    LPC_EMC->DYNAMICDAL = 7;
  422.  
  423.    LPC_EMC->DYNAMICWR    = 4;
  424.  
  425.    LPC_EMC->DYNAMICRC   = 9;
  426.  
  427.    LPC_EMC->DYNAMICRFC = 9;
  428.  
  429.    LPC_EMC->DYNAMICXSR = 9;
  430.  
  431.    LPC_EMC->DYNAMICRRD = 4;
  432.  
  433.    LPC_EMC->DYNAMICMRD = 2;
  434.  
  435.    WaitState(10000);
  436.  
  437.    LPC_EMC->DYNAMICCONTROL    = 0x00000183;  /* Issue NOP command              */
  438.  
  439.    WaitState(10000);
  440.  
  441.    LPC_EMC->DYNAMICCONTROL    = 0x00000103;  /* Issue PALL command             */
  442.  
  443.    WaitState(10000);
  444.  
  445.    LPC_EMC->DYNAMICCONTROL    = 0x00000183;  /* Issue NOP command              */
  446.  
  447.    WaitState(10000);
  448.  
  449.    LPC_EMC->DYNAMICREFRESH    = 2;   //EMC_NANOSEC(  200, SystemCoreClock, div) / 16 + 1;
  450.  
  451.    WaitState(10000);
  452.  
  453.    LPC_EMC->DYNAMICREFRESH    = 110; //EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1;
  454.  
  455.    WaitState(10000);
  456.  
  457.    LPC_EMC->DYNAMICCONTROL    = 0x00000083;  /* Issue MODE command             */
  458.  
  459.  
  460.  
  461.    /* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3   */
  462.  
  463.     uint32_t ConfigRead;
  464.     //ConfigRead=*((volatile uint32_t *)(0x28000000|0x32<<12)); //DYSC0 Base Address + MODE << OFFSET
  465.     ConfigRead=*((volatile uint32_t *)(0x28032000)); //DYSC0 Base Address + MODE << OFFSET
  466.  
  467.    // Follow with at least 2 NOPS
  468.  
  469.    LPC_EMC->DYNAMICCONTROL |=  (0x3<<7);
  470.  
  471.    LPC_EMC->DYNAMICCONTROL |=  (0x3<<7);
  472.  
  473.    LPC_EMC->DYNAMICCONTROL  = 0x00000003;  /* Issue NORMAL command               */
  474.  
  475.    LPC_EMC->DYNAMICCONFIG0 |= (1 << 19);   /* Enable buffer                      */
  476.  
  477.    LPC_EMC->STATICCONFIG0  |= (1 << 19) ;  /* Enable buffer                      */
  478.  
  479.  
  480. }
  481.  
  482.  
  483.  
  484. #define EMC_B_ENABLE                    (1 << 19)
  485. #define EMC_ENABLE                      (1 << 0)
  486. #define EMC_CE_ENABLE                   (1 << 0)
  487. #define EMC_CS_ENABLE                   (1 << 1)
  488. #define EMC_CLOCK_DELAYED_STRATEGY      (0 << 0)
  489. #define EMC_COMMAND_DELAYED_STRATEGY    (1 << 0)
  490. #define EMC_COMMAND_DELAYED_STRATEGY2   (2 << 0)
  491. #define EMC_COMMAND_DELAYED_STRATEGY3   (3 << 0)
  492. #define EMC_INIT(i)                     ((i) << 7)
  493. #define EMC_NORMAL                      (0)
  494. #define EMC_MODE                        (1)
  495. #define EMC_PRECHARGE_ALL               (2)
  496. #define EMC_NOP                         (3)
  497.  
  498. void emc_WaitUS(volatile uint32_t us)
  499. {
  500.     us *= (SystemCoreClock / 1000000) / 3;
  501.     while(us--);
  502. }
  503.  
  504. void vEMC_InitSRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits)
  505. {
  506.  
  507.     if(u32DataBus == 0)   // burst size 8, CAS3
  508.     {
  509.         *((volatile uint32_t *)(u32BaseAddr | ((3UL | (3UL << 4)) << (u32ColAddrBits + 2 + 1))));
  510.     }
  511.     else   // 32-bit, burst size 4, CAS3
  512.     {
  513.         *((volatile uint32_t *)(u32BaseAddr | ((2UL | (3UL << 4)) << (u32ColAddrBits + 2 + 2)))); //
  514.     }
  515.  
  516.     LPC_EMC->DYNAMICCONTROL     = 0; // EMC_CE_ENABLE | EMC_CS_ENABLE;
  517.     LPC_EMC->DYNAMICCONFIG0     = ((u32Width << 7) | (u32Size << 9)/* | (1UL << 12)*/ | (u32DataBus << 14)) | EMC_B_ENABLE;
  518.     LPC_EMC->DYNAMICCONFIG1     = ((u32Width << 7) | (u32Size << 9)/* | (1UL << 12)*/ | (u32DataBus << 14)) | EMC_B_ENABLE;
  519.     LPC_EMC->DYNAMICCONFIG2     = ((u32Width << 7) | (u32Size << 9)/* | (1UL << 12)*/ | (u32DataBus << 14)) | EMC_B_ENABLE;
  520.     LPC_EMC->DYNAMICCONFIG3     = ((u32Width << 7) | (u32Size << 9)/* | (1UL << 12)*/ | (u32DataBus << 14)) | EMC_B_ENABLE;
  521. }
  522.  
  523.  
  524.  
  525. void MyEMCConfig()
  526. {
  527.  
  528.     /**
  529.  * @brief   Configure clock pin function (pins SFSCLKx)
  530.  * @param   clknum  : Clock pin number, should be: 0..3
  531.  * @param   mode    : OR'ed values or type SCU_MODE_*
  532.  * @param   func    : Pin function, value of type SCU_MODE_FUNC0 to SCU_MODE_FUNC7
  533.  * @return  Nothing
  534.  */
  535.  
  536.  
  537.     uint32_t WaitN=10000;
  538.     uint32_t *pConfig; //Register pointer
  539.     /**Enable EMC clocking*/
  540.     Chip_SCU_ClockPinMuxSet(0,SCU_MODE_FUNC0); //CLK0 pad N5 set to EMC_CLOCK 0
  541.  
  542.     pConfig=(volatile uint32_t *)0x40086C00;
  543.     *pConfig|=(0x1<<6);
  544.     pConfig=(volatile uint32_t *)0x40086C04;
  545.     *pConfig|=(0x1<<6);
  546.     pConfig=(volatile uint32_t *)0x40086C08;
  547.     *pConfig|=(0x1<<6);
  548.     pConfig=(volatile uint32_t *)0x40086C0C;
  549.     *pConfig|=(0x1<<6);
  550.  
  551.  
  552.  
  553.  
  554.  
  555.     //Set CREG6 control register for EMC_CLK_SEL (bit # 16) = 1 => EMC_CLK_DIV divided by 2.
  556.     LPC_CREG->CREG6 |= 1 << 16;
  557.  
  558.     //Set CCU1 branch clock configuration register. Clock divider value (bit 5:7) 0x1 (divided by 2)
  559.     pConfig=(volatile uint32_t *)0x40051478;
  560.     *pConfig|=0x23; //bit 0,1 and 5 is 1
  561.  
  562.  
  563.  
  564.     //Configure EMCCLKDELAY for frequencies above 95 Mhz
  565.     pConfig=(volatile uint32_t *)0x40086D00;    //EMC clock delay register
  566.     *pConfig |= 0x7FFF; //~ 3.5 ns delay. Page 429
  567.  
  568.  
  569.     /**Enable the EMC interface and set EMC endian-ness*/
  570.     pConfig=(volatile uint32_t *)0x40005000; //EMC Control register
  571.     *pConfig |= 0x1;                         //Enable EMC and set normal memory map
  572.     pConfig=(volatile uint32_t *)0x40005008; //EMC Configuration register
  573.     *pConfig |= 0x0;                         //Bit 0: Endianess. 0 for little-endian (POR value)
  574.  
  575.  
  576.     /**Set a long period for the dynamic refresh rate*/
  577.     pConfig=(volatile uint32_t *)0x40005024; //Dynamic Memory Refresh Timer Register
  578.     *pConfig |= 0x7FF;                       //Long refresh period
  579.  
  580.     /**Setup address mapping*/
  581.     pConfig=(volatile uint32_t *)0x40005100;    //Dynamic Memory Configuration Register
  582.     *pConfig |= 0x6 << 7;                       //AM0 Address mapping bit 7:12
  583.     *pConfig |= 0x1 << 14;                      //AM1 Address mapping bit 14
  584.     WaitState(WaitN);                           //Empty for-loop for WaitN iterations
  585.  
  586.     //Ends up 0x4300 => RBC mapping as expected
  587.  
  588.     /**Setup RAS and CAS latencies*/
  589.     pConfig=(volatile uint32_t *)0x40005104;   //Dynamic Memory RAS & CAS Delay registers
  590.     *pConfig |= 0x3;                           //RAS 3 bit 0:1
  591.     *pConfig |= 0x3 << 8;                      //CAS 3 bit 8:9
  592.     WaitState(WaitN);                          //Empty for-loop for WaitN iterations
  593.  
  594.     /**Setup the SDRAM command and read strategy*/
  595.     pConfig=(volatile uint32_t *)0x40005028; //Dynamic Memory Read Configuration register
  596.     *pConfig |= 0x1;                         //0x1 for SDRAM operation
  597.  
  598.     /**Setup interface timing*/
  599.     LPC_EMC->DYNAMICRP      = 4;
  600.  
  601.     LPC_EMC->DYNAMICRAS     = 7;
  602.  
  603.     LPC_EMC->DYNAMICSREX    = 9;
  604.  
  605.     LPC_EMC->DYNAMICAPR     = 1;
  606.  
  607.     LPC_EMC->DYNAMICDAL     = 7;
  608.  
  609.     LPC_EMC->DYNAMICWR      = 4;
  610.  
  611.     LPC_EMC->DYNAMICRC      = 9;
  612.  
  613.     LPC_EMC->DYNAMICRFC     = 9;
  614.  
  615.     LPC_EMC->DYNAMICXSR     = 9;
  616.  
  617.     LPC_EMC->DYNAMICRRD     = 4;
  618.  
  619.     LPC_EMC->DYNAMICMRD     = 2;
  620.  
  621.  
  622.     /**Enable SDRAM clocks and clock enables and issues NOPs for 200 us*/
  623.     pConfig=(volatile uint32_t *)0x40005020; //Dynamic Control Register
  624.     *pConfig |= 0x1;                         //Clock enable
  625.     *pConfig |= 0x1 << 1;                    //Clock Control enable
  626.  
  627.     pConfig=(volatile uint32_t *)0x40005000; //EMC Control register
  628.     *pConfig |= 0x3 <<7;                     //NOP
  629.     WaitState(WaitN);
  630.  
  631.     /**Step 13: Issue precharge-all command*/
  632.     pConfig=(volatile uint32_t *)0x40005020; //Dynamic Control Register
  633.     *pConfig |= 0x1;                         //Clock enable
  634.     *pConfig |= 0x1 << 1;                    //Clock Control enable
  635.  
  636.  
  637.     pConfig=(volatile uint32_t *)0x40005024;   //Dynamic Memory Refresh Timer Register
  638.     *pConfig = 0x001;                          //Short refresh period
  639.  
  640.     pConfig=(volatile uint32_t *)0x40005020;  //EMC Control register
  641.     *pConfig |= 0x2 <<7;                      //PALL
  642.  
  643.     WaitState(WaitN);
  644.  
  645.  
  646.     /**Set normal dynamic refresh timing*/
  647.     pConfig=(volatile uint32_t *)0x40005024; //Dynamic Memory Refresh Timer Register
  648.     *pConfig |= 0x64;                        //0x64 EMC_CLK cycles => ~ 15.6 us
  649.  
  650.     /**Issue mode word*/
  651.     uint32_t ConfigRead;
  652.     //ConfigRead=*((volatile uint32_t *)(0x28000000|0x32<<12)); //DYSC0 Base Address + MODE << OFFSET
  653.     ConfigRead=*((volatile uint32_t *)(0x28032000)); //DYSC0 Base Address + MODE << OFFSET
  654.  
  655.     pConfig=(volatile uint32_t *)0x40005000; //EMC Control register
  656.     *pConfig |= 0x3 <<7;                     //NOP
  657.     WaitState(WaitN);
  658.     *pConfig |= 0x3 <<7;                     //NOP
  659.     WaitState(WaitN);
  660.  
  661.     /**Enter normal operational mode*/
  662.     pConfig=(volatile uint32_t *)0x40005020; //Dynamic Control Register
  663.     //*pConfig |= 0x00 << 7;                    //Normal mode (bit 7:8)
  664.     //*pConfig |= 0x0  << 2;                    //Self-refresh normal
  665.     *pConfig = 0x00;                            //Clear
  666.     *pConfig = 0x7;                             //CE, CS, SR
  667.  
  668.     /** Enable buffer*/
  669.     pConfig=(volatile uint32_t *)0x40005100;    //Dynamic Memory Configuration Register
  670.     *pConfig |= 0x1 << 19;
  671. }
  672.  
  673. void WaitState(uint16_t cnt)
  674. {
  675.     uint16_t i,x;
  676.     for(i=0; i<cnt; i++)
  677.     {
  678.         x++;
  679.     }
  680. }
  681.  
  682. /* Set up and initialize hardware prior to call to main */
  683. void Board_SystemInit(void)
  684. {
  685.     /* Setup system clocking and memory. This is done early to allow the
  686.        application and tools to clear memory and use scatter loading to
  687.        external memory. */
  688.     Board_SetupMuxing();
  689.     Board_SetupClocking();
  690.     MyEMCConfig();
  691.  
  692.     //Board_SetupExtMemory();
  693.  
  694. }
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