Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- void ConfigureSPIFlash()
- {
- MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
- MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1);
- // Enable pin PD2 for SSI1 SSI1RX
- MAP_GPIOPinConfigure(GPIO_PD2_SSI1RX);
- MAP_GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_2);
- // Enable pin PD0 for SSI1 SSI1CLK
- MAP_GPIOPinConfigure(GPIO_PD0_SSI1CLK);
- MAP_GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_0);
- // Enable pin PD1 for Chip Enable
- MAP_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_1);
- MAP_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_1, GPIO_PIN_1);
- // Enable pin PD3 for SSI1 SSI1TX
- MAP_GPIOPinConfigure(GPIO_PD3_SSI1TX);
- MAP_GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_3);
- MAP_SSIConfigSetExpClk(SSI1_BASE, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 125000, 8);
- MAP_SSIEnable(SSI1_BASE);
- uint32_t r;
- while(SSIDataGetNonBlocking(SSI1_BASE, &r)){}
- }
- unsigned char SPI_transmit(unsigned char data)
- {
- SSIDataPut(SSI1_BASE, data);
- uint32_t r;
- SSIDataGet(SSI1_BASE, &r);
- return (unsigned char)r;
- }
- void main(void)
- {
- ROM_FPUEnable();
- ROM_FPULazyStackingEnable();
- SysCtlClockSet(SYSCTL_SYSDIV_4| SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ |SYSCTL_OSC_MAIN);
- ConfigureUART();
- ConfigureSPIFlash();
- UARTprintf("spi flash readyn");
- uint8_t res;
- // send Read-ID command
- GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_1, ~GPIO_PIN_1); // CE low
- SPI_transmit(0x90);
- SPI_transmit(0x00);
- SPI_transmit(0x00);
- SPI_transmit(0x01);
- // get response
- res = SPI_transmit(0xff);
- UARTprintf("received: 0x%xn", res);
- GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_1, GPIO_PIN_1); // CE high
- }
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement