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-- Company:
-- Engineer:
--
-- Create Date:    16:36:31 11/22/2016
-- Design Name:
-- Module Name:    counterImp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counterImp is
    Port ( x : in  STD_LOGIC :='0';
              clock: in std_logic :='0';
              output : out std_logic_vector(3 downto 0));
end counterImp;

architecture Behavioral of counterImp is

signal z : std_logic_vector(3 downto 0) :="1001";
signal count : integer range 0 to 1025:= 0;

begin

output <= z;
process (clock)
    begin
        if(rising_edge(clock)) then
            count <= count + 1;
            if (count = 1024) then
                count <= 0;
            end if;
            if (count = 0) then
                if (x = '0') then
                    if (z = "1001") then
                        z <= "0000";
                    else
                        z <= z + 1;
                    end if;
                else
                    if (z = "0000") then
                        z <= "1001";
                    else
                        z <= z - 1;
                    end if;
                end if;
            end if;
        end if;
end process;
end Behavioral;