module CPU(input clk, input reset, inout wire[7:0] Databus,
	output wire [7:0] AdrsBus, output reg CS, output reg RW);

reg[3:0] ps, ns;

reg[7:0] PC, IR, IR2, AC, CC, MA, MD;
wire[7:0] ABus,DBus;
reg PC_IR2 ,PC_ld, PC_inc, PC_clr,
 IR_ld, IR_dec, IR2_lc,
AC_clr, AC_ld, AC_MD,
 CC_clr, CC_cf, CC_zf,
 MA_ld, MA_clr,
 MD_ld, MD_rcv, MD_snd;

assign AdrsBus = MA;
assign DataBus = MD_snd ? MD : 8'dz;
assign ABus = PC_IR2 ? PC : IR2;
assign DBus = AC_MD ? AC: MD;

reg[2:0] ALU_cmd;
wire[7:0] Result;
ALU alu(AC, IR2, CC[7], ALU_cmd, Result, CF, ZF);

always@(posedge clk)
if (reset) ps = 0;
else ps <= ns;

always@* begin
PC_IR2 = 0; PC_ld = 0; PC_inc = 0; PC_clr = 0;
IR_ld = 0; IR_dec = 0; IR2_ld = 0;
AC_clr = 0; AC_ld = 0; AC_MD = 0;
CC_clr = 0; CC_cf = 0; CC_zf = 0;
MA_ld = 0; MA_clr = 0;
MD_ld = 0; MD_rcv=0; MD_snd = 0;
ALU_cmd = 0;
ns = 1;
case (ps)
0: begin
PC_clr =1, MA_clr = 1, AC_clr = 1, CC_clr = 1;
end
1: begin
PC_inc = 1;MA_ld = 1;ns = 2;
end
2: begin
PC.inc = 1; MA_ld = 1; MD_rcv= 1;ns = 3;
end
3: begin
IR_ld = 1; MD_rcv = 1;ns = 4;
end
4: begin
IR2_ld.h;
if ( IR[7:5] == 001 || IR[7:5] == 010 || IR[7:5] == 011)
	if (IR[4:3] == 10)
	case(IR[7:5])
	3'd0 : ns = 7;
	3'd1 : ns = 8;
	3'd2 : ns = 9;
	3'd3 : ns = 10;
	3'd4 : ns = 11;
	3'd5 : ns = 12;
	3'd6 : ns = 13;
	3'd7 :
	if (CC[6]) ns = 14;
	else ns = 1;
	endcase
	else ns = 5;
else if (IR[4:3] ==01)
	case (IR[7:5])
	3'd0 : ns = 7;
	3'd1 : ns = 8;
	3'd2 : ns = 9;
	3'd3 : ns = 10;
	3'd4 : ns = 11;
	3'd5 : ns = 12;
	3'd6 : ns = 13;
	3'd7 :
	if (CC[6]) ns = 14;
	else ns = 1;
	endcase
	else ns = 5;
end
5: begin
MA_ld.h; IR_dec.h;ns = 6;
end
6: begin
MD_rcv.h; ns = 4;
end
7: begin
ALU_cmd =  3'd0; CC_zf.h;
end
8: begin
MA_ld.h;MD_ld.h;
end
9: begin
ALU_cmd = 3'd1;CC_cf.h; CC_zf.h;
end
10: begin
PC_ld.h;
end
11: begin
ALU_cmd = 3'd2;CC_zf.h;
end
12: begin
ALU_cmd = 3'd3; CC_zf.h;
end
13: begin
ALU_cmd = 3'd4;CC_zf.h;
end
14:
PC_ld.h;
15:
MD_snd.h;
endcase
end

always@(posedge clk)
if (PC_clr) PC <= 0;
else if (PC_ld) PC<=ABus;
else if (PC_inc) PC <= PC+1;
always@(posedge clk)
if (IR_ld) IR<= DBus;
else if (IR_dec) IR[4:3]<= IR[4:3] - 1;
always@(posedge clk)
if (IR2_ld) IR2<=DBus;
always@(posedge clk)
if(AC_clr) AC<=0;
else if (AC_ld) AC<=Result;

always@(posedge clk)
if (CC_clr) CC<=0;
else if (CC_cf) CC[7] <= CF;
else if (CC_zf) CC[6] <= ZF;

always@(posedge clk)
if(MA_ld) MA<= ABus;
else if (MA_clr) MA<= 0;

always@(posedge clk)
if(MD_ld) MD<=DBus;
else if (MD_rcv) MD <= DataBus;

always@(posedge clk)
case(ps)
1: CS<= 1;
2: CS<= 1;
5: CS<= 1;
6: CS<= 1;
default: CS<= 0;
endcase

always@(posedge clk)
case(ps)
8: RW<= 0;
default: RW<=1;
endcase

endmodule


module ALU(input[7:0] A, input[7:0] B, input Ci, input[3:0] cmd,
output reg[7:0]  R, output reg Co, output Z);

always@* begin
Co = 0; R = 0;
case(cmd)
3'd0: begin
R = B; Co = Ci;
end
3'd1: begin
{Co,R} = A+B;
end
3'd2: R = A|B;
3'd3: R = A&B;
3'd4: R = A^B;
endcase
end

assign Z = (R==0);
endmodule

module TestCPU;
  reg clk; reg reset; wire [7:0] AdrsBus; wire [7:0] DataBus;
  wire CS; wire RW;
CPU uut (.clk(clk), .reset(reset), .AdrsBus(AdrsBus), .DataBus(DataBus),
    .CS(CS), .RW(RW));
  initial
    forever begin
      #50; CLOCK = ~CLOCK;
    end

  reg [7:0] Buffer;
  assign DataBus = Buffer;

reg [7:0] Core [0:255];
  always@*
    if (CS==1) // Chip enabled
      if (RW==1) begin
        #75; Buffer = Core[AdrsBus]; // Read from RAM
      end
      else begin
        Buffer = 8'dZ; #75; Core[AdrsBus] = DataBus; // Write to RAM
      end
    else
      Buffer = 8'dZ;

initial begin
    clk = 0; reset = 0;
    #1000;     $readmemh("C:\Users\Tea\Downloads\CPU2.txt", Core);
    #25;       reset = 1; #100; reset = 0;
               $monitor("RAM[30] =%d", Core[30]);
    #100000;   $stop;
  end