library ieee;
use ieee.std_logic_1164.all;

entity mod_m_counter_tb is
end mod_m_counter_tb;

architecture tb of mod_m_counter_tb is

    component mod_m_counter
        port (  clk,reset   : in std_logic;
                to_m_in     : in std_logic_vector(17 downto 0);
                max_tick    : out std_logic
              );
    end component;

    --inputs
    signal clk, reset       : std_logic;
    signal to_m_in          : std_logic_vector (17 downto 0);
    --outputs
    signal max_tick: std_logic;

    constant clk_period : time := 10 ns;

begin
   uut: entity work.mod_m_counter(arch)
      port map(clk=>clk, reset=>reset,to_m_in=>to_m_in,
               max_tick=>max_tick);

   --**************************
   -- clock
   --**************************
   clk_process: process
   begin
      clk <= '0';
      wait for clk_period/2;
      clk <= '1';
      wait for clk_period/2;
   end process;

   stim_proc: process
       begin
            to_m_in <= "000000000000000000";
            reset <= '0';
            wait for clk_period*2;
            reset <= '0';

            to_m_in <= "000000000000000011";

            wait for clk_period*4;


   end process ;
end tb;