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By: a guest on Apr 17th, 2012  |  syntax: None  |  size: 0.46 KB  |  views: 13  |  expires: Never
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  1. reg [1:0] foo;
  2. reg bar;
  3. always @(posedge clk) begin
  4.         foo = a + b;
  5.         if(|foo)
  6.                 bar = 1;
  7. end
  8.  
  9. (then read foo and bar in another block)
  10.  
  11. ===>
  12.  
  13. reg [1:0] v_foo;
  14. reg v_bar;
  15. reg [1:0] foo;
  16. reg bar;
  17. always @(posedge clk) begin
  18.         v_foo = a + b;
  19.         if(|v_foo)
  20.                 v_bar = 1;
  21.         foo <= v_foo;
  22.         bar <= v_bar;
  23. end
  24.  
  25. (make sure you use v_* signals _only_ in this block. all VHDL does is enforce this using the "variable" which is really just a process-local signal)
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