module mymodule(clk, clrn, din, div)
    input clk;
    input clrn;
    input din;
    output div[1:0];

    reg clk;
    reg clrn;
    reg din;
    reg div[1:0];
    reg d1;
    reg d2;

    `DEFINE START 0
    `DEFINE FIRST 1
    `DEFINE SECOND 2
    `DEFINE STOP 3

    reg status[1:0];

    // on start

    always @ (posedge clk or posedge clrn)
    begin
    if (clrn)
    begin
        div <= 0;
        state <= `START;
    end else
    begin
        case (state)
        begin
        `START:
            if(din == 0)
            begin
                state <= `FIRST;
            end
            else
            begin
                state <= `START;
            end
        `FIRST:
            d1 <= din;
            state <= `SECOND;
        `SECOND
            d2 <= din;
            state <= `STOP;
        `STOP
            if(din == 1)
            begin
                div <= {d2, d1};
            end
            state <= `START;

        endcase
    end
endmodule