Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "F:/Users/nexys2_test2/test2.xst" -ofn "F:/Users/nexys2_test2/test2.syr"
Reading design: test2.prj

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "test2.v" in library work
Module <hex_to_sseg> compiled
Module <test2> compiled
ERROR:HDLCompilers:247 - "test2.v" line 11 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "test2.v" line 11 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "test2.v" line 12 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "test2.v" line 12 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "test2.v" line 13 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "test2.v" line 13 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "test2.v" line 14 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "test2.v" line 14 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "test2.v" line 15 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "test2.v" line 15 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "test2.v" line 16 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "test2.v" line 16 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "test2.v" line 17 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "test2.v" line 17 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "test2.v" line 18 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "test2.v" line 18 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "test2.v" line 19 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "test2.v" line 19 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "test2.v" line 20 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "test2.v" line 20 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "test2.v" line 21 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "test2.v" line 21 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "test2.v" line 22 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "test2.v" line 22 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "test2.v" line 23 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "test2.v" line 23 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "test2.v" line 24 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "test2.v" line 24 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "test2.v" line 25 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "test2.v" line 25 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "test2.v" line 26 Reference to vector wire 'sseg' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "test2.v" line 26 Illegal left hand side of blocking assignment
Analysis of file <"test2.prj"> failed.
-->

Total memory usage is 228316 kilobytes

Number of errors   :   32 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)


Process "Synthesize - XST" failed