module fsm(input reset,
           input clock,
           input R0,
           input R1,
            output reg G0,
            output reg G1);

parameter[1:0]  // synopsys enum states
S0=2'b00,
S1=2'b01,
S2=2'b10,
S3=2'b11;

reg [1:0]  /* synopsys enum states */ current_state, next_state;
// synopsys state_vector current_state

/* Sequential Logic */
always @(posedge clock or negedge reset)
    begin
        if(!reset) current_state<=S0;
        else current_state<=next_state;
    end

/*output logic and next stage logic */
always@(current_state or R0 or R1 )
    begin
        G0=0;G1=0; //default's to prevent latches
        case(current_state) // synopsys full_case parallel_case
            S0: begin
                    G0=0;G1=0;
                    case({R0,R1})
                        2'b00:next_state=S0;
                        2'b10:next_state=S1;
                        2'b01:next_state=S2;
                        2'b11:next_state=S3;

                    endcase
                end
            S1: begin
                    G0=1;G1=0;
                    case({R0,R1})
                        2'b00:next_state=S0;
                        2'b10:next_state=S1;
                        2'b01:next_state=S2;
                        2'b11:next_state=S3;
                    endcase
                end
            S2: begin
                    G0=0;G1=1;
                    case({R0,R1})
                        2'b00:next_state=S0;
                        2'b10:next_state=S1;
                        2'b01:next_state=S2;
                        2'b11:next_state=S3;
                    endcase
                end
            S3: begin
                    G0=1;G1=0;
                    next_state=S2;
                end
            default:next_state=S0;

        endcase
    end

endmodule