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- module divideclock(clkin, clkout);
- input clkin;
- output clkout;
- reg count = 'd0;
- reg n = 'd3; //Determinar valor pelo qual o clock será dividido, n = 3 como exemplo
- reg clkout;
- always@(posedge clkin)
- begin
- if (count == n)
- begin
- clkout = 1;
- count = 'd0;
- end
- else
- begin
- count = count + 1;
- clkout = 0;
- end
- end
- endmodule
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