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Verilog

By: a guest on Mar 22nd, 2013  |  syntax: VeriLog  |  size: 1.06 KB  |  views: 36  |  expires: Never
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  1. module datapath(output reg [31:15]p_high,
  2.                 output reg [14:0]p_low,
  3.                 input [15:0]x, y,
  4.                input clk); // reset, start, x_ce, y_ce, y_load_en, p_reset,
  5.                 //output done);
  6.                
  7. reg [15:0]q0;
  8. reg [15:0]q1;
  9. reg [15:0]and_output;
  10. reg [16:0]sum, prev_sum;
  11. reg d_in;
  12. reg [3:0] count_er;
  13.  
  14. initial
  15. begin
  16. count_er <= 0;
  17. sum <= 17'b0;
  18. and_output <= 0;
  19. end
  20.  
  21. always@*
  22. begin
  23.         and_output <= q0[count_er] & q1;
  24.         sum <= and_output + sum;    
  25.         d_in <= p_high[15];
  26. end
  27.  
  28. always@(posedge clk)
  29. begin
  30.         q0 <= y;
  31.         q1 <= x;
  32.         p_high <= sum;
  33.         p_low[14] <= d_in;
  34.         p_low <= p_low >> 1;
  35.         count_er <= count_er + 1;
  36. end
  37. endmodule