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jedroid_bct_cfg

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Dec 1st, 2015
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  1. # CFG Version 01#
  2. # Do not edit. Generated by T124_emc_reg_tool5.0.17.exe V5.0.17. Command:
  3. # T124_emc_reg_tool5.0.17.exe -i ddr3_256Mx16x4_H5TC4G63AFR_RDA_2GB.par -b PM358_Hynix_2GB_H5TC4G63AFR_RDA_924MHz.txt 1.082251082251082
  4. # -dram_board_cfg 10 -fly_by_time_ps 1650 -o PM375_Hynix_2GB_H5TC4G63AFR_RDA_924MHz.cfg
  5. # Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA_2GB.par, tck = 1.08 ns (924.00 MHz)
  6. # bkv file: PM358_Hynix_2GB_H5TC4G63AFR_RDA_924MHz.txt
  7. SDRAM[0].MemoryType = NvBootMemoryType_Ddr3;
  8. SDRAM[0].PllMInputDivider = 0x00000001;
  9. SDRAM[0].PllMFeedbackDivider = 0x0000004d;
  10. SDRAM[0].PllMStableTime = 0x0000012c;
  11. SDRAM[0].PllMSetupControl = 0x00000000;
  12. SDRAM[0].PllMKCP = 0x00000000;
  13. SDRAM[0].PllMKVCO = 0x00000000;
  14. SDRAM[0].EmcBctSpare0 = 0x00000000;
  15. SDRAM[0].EmcBctSpare1 = 0x00000000;
  16. SDRAM[0].EmcBctSpare2 = 0x00000000;
  17. SDRAM[0].EmcBctSpare3 = 0x00000000;
  18. SDRAM[0].EmcBctSpare4 = 0x00000000;
  19. SDRAM[0].EmcBctSpare5 = 0x00000000;
  20. SDRAM[0].EmcBctSpare6 = 0x00000000;
  21. SDRAM[0].EmcBctSpare7 = 0x00000000;
  22. SDRAM[0].EmcBctSpare8 = 0x00000000;
  23. SDRAM[0].EmcBctSpare9 = 0x00000000;
  24. SDRAM[0].EmcBctSpare10 = 0x00000000;
  25. SDRAM[0].EmcBctSpare11 = 0x00000000;
  26. SDRAM[0].EmcClockSource = 0x80000000;
  27. SDRAM[0].EmcAutoCalInterval = 0x001fffff;
  28. SDRAM[0].EmcAutoCalConfig = 0xa1430303;
  29. SDRAM[0].EmcAutoCalConfig2 = 0x00000000;
  30. SDRAM[0].EmcAutoCalConfig3 = 0x00000000;
  31. SDRAM[0].EmcAutoCalWait = 0x00000190;
  32. SDRAM[0].EmcAdrCfg = 0x00000000;
  33. SDRAM[0].EmcPinProgramWait = 0x00000001;
  34. SDRAM[0].EmcPinExtraWait = 0x00000000;
  35. SDRAM[0].EmcTimingControlWait = 0x00000000;
  36. SDRAM[0].EmcRc = 0x0000002b;
  37. SDRAM[0].EmcRfc = 0x000000f0;
  38. SDRAM[0].EmcRfcSlr = 0x00000000;
  39. SDRAM[0].EmcRas = 0x0000001e;
  40. SDRAM[0].EmcRp = 0x0000000b;
  41. SDRAM[0].EmcR2r = 0x00000000;
  42. SDRAM[0].EmcW2w = 0x00000000;
  43. SDRAM[0].EmcR2w = 0x00000009;
  44. SDRAM[0].EmcW2r = 0x0000000f;
  45. SDRAM[0].EmcR2p = 0x00000005;
  46. SDRAM[0].EmcW2p = 0x00000016;
  47. SDRAM[0].EmcRdRcd = 0x0000000b;
  48. SDRAM[0].EmcWrRcd = 0x0000000b;
  49. SDRAM[0].EmcRrd = 0x00000004;
  50. SDRAM[0].EmcRext = 0x00000002;
  51. SDRAM[0].EmcWext = 0x00000000;
  52. SDRAM[0].EmcWdv = 0x00000007;
  53. SDRAM[0].EmcWdvMask = 0x00000007;
  54. SDRAM[0].EmcQUse = 0x0000000d;
  55. SDRAM[0].EmcQuseWidth = 0x00000002;
  56. SDRAM[0].EmcIbdly = 0x00000000;
  57. SDRAM[0].EmcEInput = 0x00000002;
  58. SDRAM[0].EmcEInputDuration = 0x0000000f;
  59. SDRAM[0].EmcPutermExtra = 0x000a0000;
  60. SDRAM[0].EmcPutermWidth = 0x00000004;
  61. SDRAM[0].EmcQRst = 0x00000001;
  62. SDRAM[0].EmcQSafe = 0x00000016;
  63. SDRAM[0].EmcRdv = 0x0000001a;
  64. SDRAM[0].EmcRdvMask = 0x0000001c;
  65. SDRAM[0].EmcQpop = 0x00000011;
  66. SDRAM[0].EmcRefresh = 0x00001be7;
  67. SDRAM[0].EmcBurstRefreshNum = 0x00000000;
  68. SDRAM[0].EmcPreRefreshReqCnt = 0x000006f9;
  69. SDRAM[0].EmcPdEx2Wr = 0x00000004;
  70. SDRAM[0].EmcPdEx2Rd = 0x00000015;
  71. SDRAM[0].EmcPChg2Pden = 0x00000001;
  72. SDRAM[0].EmcAct2Pden = 0x00000000;
  73. SDRAM[0].EmcAr2Pden = 0x000000e7;
  74. SDRAM[0].EmcRw2Pden = 0x0000001b;
  75. SDRAM[0].EmcTxsr = 0x000000fb;
  76. SDRAM[0].EmcTxsrDll = 0x00000200;
  77. SDRAM[0].EmcTcke = 0x00000006;
  78. SDRAM[0].EmcTckesr = 0x00000007;
  79. SDRAM[0].EmcTpd = 0x00000006;
  80. SDRAM[0].EmcTfaw = 0x0000001e;
  81. SDRAM[0].EmcTrpab = 0x00000000;
  82. SDRAM[0].EmcTClkStable = 0x0000000a;
  83. SDRAM[0].EmcTClkStop = 0x0000000a;
  84. SDRAM[0].EmcTRefBw = 0x00001c28;
  85. SDRAM[0].EmcFbioCfg5 = 0x104ab898;
  86. SDRAM[0].EmcCfgRsv = 0xff00ff00;
  87. SDRAM[0].EmcMrs = 0x80000f15;
  88. SDRAM[0].EmcEmrs = 0x80100002;
  89. SDRAM[0].EmcEmrs2 = 0x80200020;
  90. SDRAM[0].EmcEmrs3 = 0x80300000;
  91. SDRAM[0].EmcMrw1 = 0x00000000;
  92. SDRAM[0].EmcMrw2 = 0x00000000;
  93. SDRAM[0].EmcMrw3 = 0x00000000;
  94. SDRAM[0].EmcMrw4 = 0x00000000;
  95. SDRAM[0].EmcMrwExtra = 0x00000000;
  96. SDRAM[0].EmcWarmBootMrwExtra = 0x00000000;
  97. SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
  98. SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000;
  99. SDRAM[0].EmcMrwResetCommand = 0x00000000;
  100. SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
  101. SDRAM[0].EmcMrsWaitCnt = 0x00cd000e;
  102. SDRAM[0].EmcMrsWaitCnt2 = 0x00cd000e;
  103. SDRAM[0].EmcCfg = 0x73300000;
  104. SDRAM[0].EmcCfg2 = 0x0000089d;
  105. SDRAM[0].EmcCfgPipe = 0x00004080;
  106. SDRAM[0].EmcDbg = 0x01000c00;
  107. SDRAM[0].EmcCmdQ = 0x10004408;
  108. SDRAM[0].EmcMc2EmcQ = 0x06000404;
  109. SDRAM[0].EmcDynSelfRefControl = 0x800037ea;
  110. SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
  111. SDRAM[0].EmcCfgDigDll = 0xe00400b1;
  112. SDRAM[0].EmcCfgDigDllPeriod = 0x00008000;
  113. SDRAM[0].EmcDevSelect = 0x00000002;
  114. SDRAM[0].EmcSelDpdCtrl = 0x00040000;
  115. SDRAM[0].WarmBootWait = 0x00000002;
  116. SDRAM[0].EmcOdtWrite = 0x00000000;
  117. SDRAM[0].EmcZcalInterval = 0x00020000;
  118. SDRAM[0].EmcZcalWaitCnt = 0x0000004c;
  119. SDRAM[0].EmcZcalMrwCmd = 0x80000000;
  120. SDRAM[0].EmcMrsResetDll = 0x00000000;
  121. SDRAM[0].EmcZcalInitDev0 = 0x80000011;
  122. SDRAM[0].EmcZcalInitDev1 = 0x00000000;
  123. SDRAM[0].EmcZcalInitWait = 0x00000001;
  124. SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003;
  125. SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
  126. SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000;
  127. SDRAM[0].EmcZcalWarmBootWait = 0x00000001;
  128. SDRAM[0].EmcMrsWarmBootEnable = 0x00000001;
  129. SDRAM[0].EmcMrsResetDllWait = 0x00000000;
  130. SDRAM[0].EmcMrsExtra = 0x80000f15;
  131. SDRAM[0].EmcWarmBootMrsExtra = 0x80100002;
  132. SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000;
  133. SDRAM[0].EmcMrsDdr2DllReset = 0x00000000;
  134. SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000;
  135. SDRAM[0].EmcDdr2Wait = 0x00000000;
  136. SDRAM[0].EmcClkenOverride = 0x00000000;
  137. SDRAM[0].EmcExtraRefreshNum = 0x00000002;
  138. SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000;
  139. SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000;
  140. SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
  141. SDRAM[0].PmcVddpSel = 0x00000002;
  142. SDRAM[0].PmcVddpSelWait = 0x00000002;
  143. SDRAM[0].PmcDdrPwr = 0x00000003;
  144. SDRAM[0].PmcDdrCfg = 0x00002002;
  145. SDRAM[0].PmcIoDpd3Req = 0x4fff2f97;
  146. SDRAM[0].PmcIoDpd3ReqWait = 0x00000000;
  147. SDRAM[0].PmcRegShort = 0x00000000;
  148. SDRAM[0].PmcNoIoPower = 0x00000000;
  149. SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108;
  150. SDRAM[0].EmcAcpdControl = 0x00000000;
  151. SDRAM[0].EmcSwizzleRank0Byte0 = 0x01643752;
  152. SDRAM[0].EmcSwizzleRank0Byte1 = 0x34675021;
  153. SDRAM[0].EmcSwizzleRank0Byte2 = 0x63170254;
  154. SDRAM[0].EmcSwizzleRank0Byte3 = 0x14065327;
  155. SDRAM[0].EmcSwizzleRank1Byte0 = 0x73541062;
  156. SDRAM[0].EmcSwizzleRank1Byte1 = 0x10637254;
  157. SDRAM[0].EmcSwizzleRank1Byte2 = 0x62043715;
  158. SDRAM[0].EmcSwizzleRank1Byte3 = 0x73015624;
  159. SDRAM[0].EmcTxdsrvttgen = 0x00000000;
  160. SDRAM[0].McEmemAdrCfg = 0x00000000;
  161. SDRAM[0].McEmemAdrCfgDev0 = 0x00080303;
  162. SDRAM[0].McEmemAdrCfgDev1 = 0x00080303;
  163. SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248;
  164. SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490;
  165. SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920;
  166. SDRAM[0].McEmemCfg = 0x00000800;
  167. SDRAM[0].McEmemArbCfg = 0x0e00000d;
  168. SDRAM[0].McEmemArbOutstandingReq = 0x80000040;
  169. SDRAM[0].McEmemArbTimingRcd = 0x00000005;
  170. SDRAM[0].McEmemArbTimingRp = 0x00000006;
  171. SDRAM[0].McEmemArbTimingRc = 0x00000016;
  172. SDRAM[0].McEmemArbTimingRas = 0x0000000e;
  173. SDRAM[0].McEmemArbTimingFaw = 0x0000000f;
  174. SDRAM[0].McEmemArbTimingRrd = 0x00000002;
  175. SDRAM[0].McEmemArbTimingRap2Pre = 0x00000004;
  176. SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000e;
  177. SDRAM[0].McEmemArbTimingR2R = 0x00000002;
  178. SDRAM[0].McEmemArbTimingW2W = 0x00000002;
  179. SDRAM[0].McEmemArbTimingR2W = 0x00000006;
  180. SDRAM[0].McEmemArbTimingW2R = 0x00000009;
  181. SDRAM[0].McEmemArbDaTurns = 0x09060202;
  182. SDRAM[0].McEmemArbDaCovers = 0x001a1016;
  183. SDRAM[0].McEmemArbMisc0 = 0x734e2a17;
  184. SDRAM[0].McEmemArbMisc1 = 0x70000f02;
  185. SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
  186. SDRAM[0].McEmemArbOverride = 0x10000000;
  187. SDRAM[0].McEmemArbOverride1 = 0x00000000;
  188. SDRAM[0].McEmemArbRsv = 0xff00ff00;
  189. SDRAM[0].McClkenOverride = 0x00000000;
  190. SDRAM[0].McStatControl = 0x00000000;
  191. SDRAM[0].McVideoProtectBom = 0xfff00000;
  192. SDRAM[0].McVideoProtectBomAdrHi = 0x00000000;
  193. SDRAM[0].McVideoProtectSizeMb = 0x00000000;
  194. SDRAM[0].McVideoProtectVprOverride = 0xe4bac743;
  195. SDRAM[0].McVideoProtectVprOverride1 = 0x00000013;
  196. SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000;
  197. SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000;
  198. SDRAM[0].McSecCarveoutBom = 0xfff00000;
  199. SDRAM[0].McSecCarveoutAdrHi = 0x00000000;
  200. SDRAM[0].McSecCarveoutSizeMb = 0x00000000;
  201. SDRAM[0].McVideoProtectWriteAccess = 0x00000000;
  202. SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000;
  203. SDRAM[0].EmcCaTrainingEnable = 0x00000000;
  204. SDRAM[0].SwizzleRankByteEncode = 0x0000000b;
  205. SDRAM[0].BootRomPatchControl = 0x00000000;
  206. SDRAM[0].BootRomPatchData = 0x00000000;
  207. SDRAM[0].McMtsCarveoutBom = 0xfff00000;
  208. SDRAM[0].McMtsCarveoutAdrHi = 0x00000000;
  209. SDRAM[0].McMtsCarveoutSizeMb = 0x00000000;
  210. SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000;
  211. #@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000017;
  212. #@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000001bb;
  213. #@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x006e0038;
  214. #@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x006e0038;
  215. #@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x006e003c;
  216. #@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x006e0090;
  217. #@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x006e0041;
  218. #@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x006e0090;
  219. #@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x006e0041;
  220. #@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049;
  221. #@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x006e0080;
  222. #@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x006e0004;
  223. #@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x006e0004;
  224. #@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016;
  225. #@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x0000006e;
  226. #@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x006e0004;
  227. #@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x006e0019;
  228. #@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x006e0018;
  229. #@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x006e0024;
  230. #@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x006e001b;
  231. #@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x0000006e;
  232. #@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036;
  233. #@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x006e006e;
  234. #@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036;
  235. #@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x006e006e;
  236. #@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff;
  237. #@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029;
  238. #@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x006e006e;
  239. #@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x006e006e;
  240. #@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x006e0065;
  241. #@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x006e001c;
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