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-- Company:
-- Engineer:
--
-- Create Date:    15:26:09 01/10/2017
-- Design Name:
-- Module Name:    source - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity source is
port(
    prekidaci: in std_logic_vector(7 downto 0);
    desnatipka: in std_logic;
    lijevatipka: in std_logic;
    led: out std_logic_vector(6 downto 0);
    pokaz: inout std_logic_vector(3 downto 0)
    );
end source;

architecture Behavioral of source is
signal temp:std_logic_vector(3 downto 0);
begin
    with prekidaci select
        led <= "0000001" when "00000001",
                "1001111" when "00000010",
                "0010010" when "00000100",
                "0000110" when "00001000",
                "1001100" when "00010000",
                "0100100" when "00100000",
                "0100000" when "01000000",
                "0001111" when "10000000",
                "0110000" when others;
process(desnatipka)
begin
    if(desnatipka'event and desnatipka='1') then
        temp<=temp+1;
    end if;
end process;

process(lijevatipka)
begin
    if(lijevatipka'event and lijevatipka='1') then
        temp<=temp-1;
    end if;
end process;

process(temp)
begin
    case temp is
            when "00" => pokaz <= "1110";
            when "01" => pokaz <= "0111";
            when "10" => pokaz <= "1011";
            when "11" => pokaz <= "1101";
    end case;
end process;

end Behavioral;