Advertisement
Guest User

Untitled

a guest
Feb 5th, 2016
74
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 9.45 KB | None | 0 0
  1. ----------------------------------------------------------------------------------
  2. -- Company: Cal Poly San Luis Obispo
  3. -- Engineer: Hector Farias, Richard Le
  4. --
  5. -- Create Date: 01/08/2016
  6. -- Design Name:
  7. -- Module Name: FinalProgCount_test - Behavioral
  8. -- Project Name: Program Counter
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20.  
  21.  
  22. --libraries
  23. library IEEE;
  24. use IEEE.STD_LOGIC_1164.ALL;
  25.  
  26. --enitity
  27. entity Rat_CPU1 is
  28. port ( INTR_VECT : in std_logic_vector (9 downto 0) := (others => '0');
  29. d3 : in std_logic_vector (9 downto 0) := (others => '0');
  30. RST : in std_logic := '0';
  31. CLK : in std_logic;
  32. INT : in std_logic := '0';
  33. UNUSED : in std_logic_vector (7 downto 0) := (others => '0');
  34. IN_PORT : in std_logic_vector (7 downto 0) := (others => '0');
  35. SP_LD : out std_logic;
  36. SP_MUX_SEL : out std_logic_vector (1 downto 0);
  37. SP_RST : out std_logic;
  38. SCR_WR : out std_logic;
  39. SCR_OE : out std_logic;
  40. SCR_ADDR_SEL: out std_logic_vector (1 downto 0);
  41. SHAD_C_LD : out std_logic;
  42. SHAD_Z_LD : out std_logic;
  43. I_SET : out std_logic;
  44. I_CLR : out std_logic;
  45. OUT_PORT : out std_logic_vector (7 downto 0);
  46. PORT_ID : out std_logic_vector (7 downto 0);
  47. IO_OE : out std_logic
  48. );
  49. end Rat_CPU1;
  50.  
  51. --architecture
  52. architecture behavioral of Rat_CPU1 is
  53.  
  54. --components
  55. component muxQ419 is
  56. port(
  57. PC_MUX_SEL : in std_logic_vector(1 downto 0);
  58. FROM_IMMED : in std_logic_vector(9 downto 0);
  59. FROM_STACK : in std_logic_vector(9 downto 0);
  60. INTR_VECT : in std_logic_vector(9 downto 0);
  61. d3 : in std_logic_vector(9 downto 0);
  62. D_IN : out std_logic_vector(9 downto 0)
  63. );
  64. end component;
  65.  
  66. component muxQ417 is
  67. port(
  68. RF_WR_SEL : in std_logic_vector(1 downto 0);
  69. SUM : in std_logic_vector(7 downto 0);
  70. MULTI_BUS : in std_logic_vector(7 downto 0);
  71. UNUSED : in std_logic_vector(7 downto 0);
  72. IN_PORT : in std_logic_vector(7 downto 0);
  73. RF_WR_DATA : out std_logic_vector(7 downto 0)
  74. );
  75. end component;
  76.  
  77. component PCounter is
  78. port (RST : in std_logic;
  79. CLK : in std_logic;
  80. PC_LD : in std_logic;
  81. PC_INC : in std_logic;
  82. PC_OE : in std_logic;
  83. D_IN : in std_logic_vector (9 downto 0);
  84. PC_COUNT : out std_logic_vector (9 downto 0);
  85. PC_TRI : out std_logic_vector (9 downto 0)
  86. );
  87. end component;
  88.  
  89. component prog_rom2 is
  90. port ( PC_COUNT : in std_logic_vector(9 downto 0);
  91. INSTRUCTION : out std_logic_vector(17 downto 0);
  92. CLK : in std_logic);
  93. end component;
  94.  
  95. component RegisterFile is
  96. Port ( DIN : in STD_LOGIC_VECTOR (7 downto 0);
  97. DX_OUT : out STD_LOGIC_VECTOR (7 downto 0);
  98. DY_OUT : out STD_LOGIC_VECTOR (7 downto 0);
  99. ADRX : in STD_LOGIC_VECTOR (4 downto 0);
  100. ADRY : in STD_LOGIC_VECTOR (4 downto 0);
  101. DX_OE : in STD_LOGIC;
  102. WE : in STD_LOGIC;
  103. CLK : in STD_LOGIC);
  104. end component;
  105.  
  106. component muxQ21 is
  107. port( REG_IMMED_SEL : in std_logic;
  108. SY : in std_logic_vector (7 downto 0);
  109. IRpart : in std_logic_vector (7 downto 0);
  110. B : out std_logic_vector (7 downto 0)
  111. );
  112. end component;
  113.  
  114. component alu1 is
  115. port ( A : in std_logic_vector(7 downto 0);
  116. B : in std_logic_vector(7 downto 0);
  117. C_IN : in std_logic;
  118. ALU_SEL: in std_logic_vector(3 downto 0);
  119. SUM : out std_logic_vector(7 downto 0);
  120. Z_FLAG : out std_logic;
  121. C_FLAG : out std_logic
  122. );
  123. end component;
  124.  
  125. component ControlUnit is
  126. port ( CLK : in STD_LOGIC;
  127. C : in STD_LOGIC;
  128. Z : in STD_LOGIC;
  129. INT : in STD_LOGIC;
  130. RST : in STD_LOGIC;
  131. OPCODE_HI_5 : in STD_LOGIC_VECTOR (4 downto 0);
  132. OPCODE_LO_2 : in STD_LOGIC_VECTOR (1 downto 0);
  133. PC_LD : out STD_LOGIC;
  134. PC_INC : out STD_LOGIC;
  135. PC_RESET : out STD_LOGIC;
  136. PC_OE : out STD_LOGIC;
  137. PC_MUX_SEL : out STD_LOGIC_VECTOR (1 downto 0);
  138. SP_LD : out STD_LOGIC;
  139. SP_MUX_SEL : out STD_LOGIC_VECTOR (1 downto 0);
  140. SP_RESET : out STD_LOGIC;
  141. RF_WR : out STD_LOGIC;
  142. RF_WR_SEL : out STD_LOGIC_VECTOR (1 downto 0);
  143. RF_OE : out STD_LOGIC;
  144. REG_IMMED_SEL : out STD_LOGIC;
  145. ALU_SEL : out STD_LOGIC_VECTOR (3 downto 0);
  146. SCR_WR : out STD_LOGIC;
  147. SCR_OE : out STD_LOGIC;
  148. SCR_ADDR_SEL : out STD_LOGIC_VECTOR (1 downto 0);
  149. C_FLAG_SEL : out STD_LOGIC_VECTOR (1 downto 0);
  150. C_FLAG_LD : out STD_LOGIC;
  151. C_FLAG_SET : out STD_LOGIC;
  152. C_FLAG_CLR : out STD_LOGIC;
  153. SHAD_C_LD : out STD_LOGIC;
  154. Z_FLAG_SEL : out STD_LOGIC_VECTOR (1 downto 0);
  155. Z_FLAG_LD : out STD_LOGIC;
  156. Z_FLAG_SET : out STD_LOGIC;
  157. Z_FLAG_CLR : out STD_LOGIC;
  158. SHAD_Z_LD : out STD_LOGIC;
  159. I_FLAG_SET : out STD_LOGIC;
  160. I_FLAG_CLR : out STD_LOGIC;
  161. IO_OE : out STD_LOGIC);
  162. end component;
  163.  
  164.  
  165. component FlagReg is
  166. Port ( IN_FLAG : in STD_LOGIC;
  167. LD : in STD_LOGIC;
  168. SET : in STD_LOGIC;
  169. CLR : in STD_LOGIC;
  170. CLK : in STD_LOGIC;
  171. OUT_FLAG : out STD_LOGIC);
  172. end component;
  173.  
  174.  
  175. --signals
  176. signal D_IN : std_logic_vector (9 downto 0);
  177. signal PC_COUNT : std_logic_vector (9 downto 0);
  178. signal IR : std_logic_vector (17 downto 0);
  179. signal MULTI_BUS : std_logic_vector (9 downto 0);
  180. signal B : std_logic_vector (7 downto 0);
  181. signal SUM : std_logic_vector (7 downto 0);
  182. signal PC_OE : std_logic;
  183. signal PC_LD : std_logic;
  184. signal PC_INC : std_logic;
  185. signal PC_RST : std_logic;
  186. signal PC_MUX_SEL : std_logic_vector (1 downto 0);
  187. signal RF_WR_SEL : std_logic_vector (1 downto 0);
  188. signal REG_IMMED_SEL : std_logic;
  189. signal RF_WR_DATA : std_logic_vector (7 downto 0);
  190. signal ALU_SEL : std_logic_vector (3 downto 0);
  191. signal SX : std_logic_vector (7 downto 0);
  192. signal SY : std_logic_vector (7 downto 0);
  193. signal C_OUT : std_logic;
  194. signal Z_OUT : std_logic;
  195. signal C_FLAG : std_logic;
  196. signal Z_FLAG : std_logic;
  197. signal C_FLAG_SEL : std_logic_vector (1 downto 0);
  198. signal Z_FLAG_SEL : std_logic_vector (1 downto 0);
  199. signal RF_OE : std_logic;
  200. signal RF_WR : std_logic;
  201. signal C_LD :std_logic;
  202. signal C_SET :std_logic;
  203. signal C_CLR :std_logic;
  204. signal Z_LD :std_logic;
  205. signal Z_SET :std_logic;
  206. signal Z_CLR :std_logic;
  207.  
  208.  
  209. begin
  210.  
  211. --muxPC instantiation
  212. mx41 : muxQ419 port map (PC_MUX_SEL, IR(12 downto 3), MULTI_BUS(9 downto 0), INTR_VECT,
  213. d3, D_IN);
  214.  
  215. --program counter instantiation
  216. PC1 : PCounter port map (PC_RST, CLK, PC_LD, PC_INC, PC_OE, D_IN, PC_COUNT,
  217. MULTI_BUS(9 downto 0));
  218.  
  219. --prog_rom2 instantiation
  220. ProgRm : prog_rom2 port map(PC_COUNT, IR, CLK);
  221.  
  222. --ControlUnit instantiation
  223. CU1 : ControlUnit port map (CLK, C_FLAG, Z_FLAG, INT, RST, IR(17 downto 13),
  224. IR(1 downto 0), PC_LD, PC_INC, PC_RST, PC_OE, PC_MUX_SEL,
  225. SP_LD, SP_MUX_SEL, SP_RST, RF_WR, RF_WR_SEL, RF_OE,
  226. REG_IMMED_SEL, ALU_SEL, SCR_WR, SCR_OE, SCR_ADDR_SEL,
  227. C_FLAG_SEL, C_LD, C_SET, C_CLR, SHAD_C_LD,Z_FLAG_SEL,
  228. Z_LD, Z_SET, Z_CLR, SHAD_Z_LD, I_SET, I_CLR, IO_OE);
  229.  
  230. --register instantiation
  231. reg1 : RegisterFile port map (RF_WR_DATA, SX, SY,
  232. IR(12 downto 8), IR(7 downto 3), RF_OE, RF_WR, CLK);
  233.  
  234. --muxALU instantiation
  235. mx21 : muxQ21 port map (REG_IMMED_SEL, SY, IR(7 downto 0), B);
  236.  
  237. --ALU instantiation
  238. Arthlu1 : alu1 port map (SX, B, C_FLAG, ALU_SEL, SUM, C_OUT, Z_OUT);
  239.  
  240. --muxRF instantiation
  241. mx42 : muxQ417 port map (RF_WR_SEL, SUM, MULTI_BUS(7 downto 0), UNUSED, IN_PORT,
  242. RF_WR_DATA);
  243. --FlagRegC
  244. FlagC : FlagReg port map (C_OUT, C_LD, C_SET, C_CLR, CLK, C_FLAG);
  245.  
  246. --FlagRegZ
  247. FlagZ : FlagReg port map (Z_OUT, Z_LD, Z_SET, Z_CLR, CLK, Z_FLAG);
  248.  
  249. MULTI_BUS(7 downto 0) <= SX;
  250. PORT_ID <= IR(7 downto 0);
  251. OUT_PORT <= MULTI_BUS(7 downto 0);
  252. end behavioral;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement