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- ----------------------------------------------------------------------------------
- -- Company: Cal Poly San Luis Obispo
- -- Engineer: Hector Farias, Richard Le
- --
- -- Create Date: 01/08/2016
- -- Design Name:
- -- Module Name: FinalProgCount_test - Behavioral
- -- Project Name: Program Counter
- -- Target Devices:
- -- Tool Versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
- --libraries
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- --enitity
- entity Rat_CPU1 is
- port ( INTR_VECT : in std_logic_vector (9 downto 0) := (others => '0');
- d3 : in std_logic_vector (9 downto 0) := (others => '0');
- RST : in std_logic := '0';
- CLK : in std_logic;
- INT : in std_logic := '0';
- UNUSED : in std_logic_vector (7 downto 0) := (others => '0');
- IN_PORT : in std_logic_vector (7 downto 0) := (others => '0');
- SP_LD : out std_logic;
- SP_MUX_SEL : out std_logic_vector (1 downto 0);
- SP_RST : out std_logic;
- SCR_WR : out std_logic;
- SCR_OE : out std_logic;
- SCR_ADDR_SEL: out std_logic_vector (1 downto 0);
- SHAD_C_LD : out std_logic;
- SHAD_Z_LD : out std_logic;
- I_SET : out std_logic;
- I_CLR : out std_logic;
- OUT_PORT : out std_logic_vector (7 downto 0);
- PORT_ID : out std_logic_vector (7 downto 0);
- IO_OE : out std_logic
- );
- end Rat_CPU1;
- --architecture
- architecture behavioral of Rat_CPU1 is
- --components
- component muxQ419 is
- port(
- PC_MUX_SEL : in std_logic_vector(1 downto 0);
- FROM_IMMED : in std_logic_vector(9 downto 0);
- FROM_STACK : in std_logic_vector(9 downto 0);
- INTR_VECT : in std_logic_vector(9 downto 0);
- d3 : in std_logic_vector(9 downto 0);
- D_IN : out std_logic_vector(9 downto 0)
- );
- end component;
- component muxQ417 is
- port(
- RF_WR_SEL : in std_logic_vector(1 downto 0);
- SUM : in std_logic_vector(7 downto 0);
- MULTI_BUS : in std_logic_vector(7 downto 0);
- UNUSED : in std_logic_vector(7 downto 0);
- IN_PORT : in std_logic_vector(7 downto 0);
- RF_WR_DATA : out std_logic_vector(7 downto 0)
- );
- end component;
- component PCounter is
- port (RST : in std_logic;
- CLK : in std_logic;
- PC_LD : in std_logic;
- PC_INC : in std_logic;
- PC_OE : in std_logic;
- D_IN : in std_logic_vector (9 downto 0);
- PC_COUNT : out std_logic_vector (9 downto 0);
- PC_TRI : out std_logic_vector (9 downto 0)
- );
- end component;
- component prog_rom2 is
- port ( PC_COUNT : in std_logic_vector(9 downto 0);
- INSTRUCTION : out std_logic_vector(17 downto 0);
- CLK : in std_logic);
- end component;
- component RegisterFile is
- Port ( DIN : in STD_LOGIC_VECTOR (7 downto 0);
- DX_OUT : out STD_LOGIC_VECTOR (7 downto 0);
- DY_OUT : out STD_LOGIC_VECTOR (7 downto 0);
- ADRX : in STD_LOGIC_VECTOR (4 downto 0);
- ADRY : in STD_LOGIC_VECTOR (4 downto 0);
- DX_OE : in STD_LOGIC;
- WE : in STD_LOGIC;
- CLK : in STD_LOGIC);
- end component;
- component muxQ21 is
- port( REG_IMMED_SEL : in std_logic;
- SY : in std_logic_vector (7 downto 0);
- IRpart : in std_logic_vector (7 downto 0);
- B : out std_logic_vector (7 downto 0)
- );
- end component;
- component alu1 is
- port ( A : in std_logic_vector(7 downto 0);
- B : in std_logic_vector(7 downto 0);
- C_IN : in std_logic;
- ALU_SEL: in std_logic_vector(3 downto 0);
- SUM : out std_logic_vector(7 downto 0);
- Z_FLAG : out std_logic;
- C_FLAG : out std_logic
- );
- end component;
- component ControlUnit is
- port ( CLK : in STD_LOGIC;
- C : in STD_LOGIC;
- Z : in STD_LOGIC;
- INT : in STD_LOGIC;
- RST : in STD_LOGIC;
- OPCODE_HI_5 : in STD_LOGIC_VECTOR (4 downto 0);
- OPCODE_LO_2 : in STD_LOGIC_VECTOR (1 downto 0);
- PC_LD : out STD_LOGIC;
- PC_INC : out STD_LOGIC;
- PC_RESET : out STD_LOGIC;
- PC_OE : out STD_LOGIC;
- PC_MUX_SEL : out STD_LOGIC_VECTOR (1 downto 0);
- SP_LD : out STD_LOGIC;
- SP_MUX_SEL : out STD_LOGIC_VECTOR (1 downto 0);
- SP_RESET : out STD_LOGIC;
- RF_WR : out STD_LOGIC;
- RF_WR_SEL : out STD_LOGIC_VECTOR (1 downto 0);
- RF_OE : out STD_LOGIC;
- REG_IMMED_SEL : out STD_LOGIC;
- ALU_SEL : out STD_LOGIC_VECTOR (3 downto 0);
- SCR_WR : out STD_LOGIC;
- SCR_OE : out STD_LOGIC;
- SCR_ADDR_SEL : out STD_LOGIC_VECTOR (1 downto 0);
- C_FLAG_SEL : out STD_LOGIC_VECTOR (1 downto 0);
- C_FLAG_LD : out STD_LOGIC;
- C_FLAG_SET : out STD_LOGIC;
- C_FLAG_CLR : out STD_LOGIC;
- SHAD_C_LD : out STD_LOGIC;
- Z_FLAG_SEL : out STD_LOGIC_VECTOR (1 downto 0);
- Z_FLAG_LD : out STD_LOGIC;
- Z_FLAG_SET : out STD_LOGIC;
- Z_FLAG_CLR : out STD_LOGIC;
- SHAD_Z_LD : out STD_LOGIC;
- I_FLAG_SET : out STD_LOGIC;
- I_FLAG_CLR : out STD_LOGIC;
- IO_OE : out STD_LOGIC);
- end component;
- component FlagReg is
- Port ( IN_FLAG : in STD_LOGIC;
- LD : in STD_LOGIC;
- SET : in STD_LOGIC;
- CLR : in STD_LOGIC;
- CLK : in STD_LOGIC;
- OUT_FLAG : out STD_LOGIC);
- end component;
- --signals
- signal D_IN : std_logic_vector (9 downto 0);
- signal PC_COUNT : std_logic_vector (9 downto 0);
- signal IR : std_logic_vector (17 downto 0);
- signal MULTI_BUS : std_logic_vector (9 downto 0);
- signal B : std_logic_vector (7 downto 0);
- signal SUM : std_logic_vector (7 downto 0);
- signal PC_OE : std_logic;
- signal PC_LD : std_logic;
- signal PC_INC : std_logic;
- signal PC_RST : std_logic;
- signal PC_MUX_SEL : std_logic_vector (1 downto 0);
- signal RF_WR_SEL : std_logic_vector (1 downto 0);
- signal REG_IMMED_SEL : std_logic;
- signal RF_WR_DATA : std_logic_vector (7 downto 0);
- signal ALU_SEL : std_logic_vector (3 downto 0);
- signal SX : std_logic_vector (7 downto 0);
- signal SY : std_logic_vector (7 downto 0);
- signal C_OUT : std_logic;
- signal Z_OUT : std_logic;
- signal C_FLAG : std_logic;
- signal Z_FLAG : std_logic;
- signal C_FLAG_SEL : std_logic_vector (1 downto 0);
- signal Z_FLAG_SEL : std_logic_vector (1 downto 0);
- signal RF_OE : std_logic;
- signal RF_WR : std_logic;
- signal C_LD :std_logic;
- signal C_SET :std_logic;
- signal C_CLR :std_logic;
- signal Z_LD :std_logic;
- signal Z_SET :std_logic;
- signal Z_CLR :std_logic;
- begin
- --muxPC instantiation
- mx41 : muxQ419 port map (PC_MUX_SEL, IR(12 downto 3), MULTI_BUS(9 downto 0), INTR_VECT,
- d3, D_IN);
- --program counter instantiation
- PC1 : PCounter port map (PC_RST, CLK, PC_LD, PC_INC, PC_OE, D_IN, PC_COUNT,
- MULTI_BUS(9 downto 0));
- --prog_rom2 instantiation
- ProgRm : prog_rom2 port map(PC_COUNT, IR, CLK);
- --ControlUnit instantiation
- CU1 : ControlUnit port map (CLK, C_FLAG, Z_FLAG, INT, RST, IR(17 downto 13),
- IR(1 downto 0), PC_LD, PC_INC, PC_RST, PC_OE, PC_MUX_SEL,
- SP_LD, SP_MUX_SEL, SP_RST, RF_WR, RF_WR_SEL, RF_OE,
- REG_IMMED_SEL, ALU_SEL, SCR_WR, SCR_OE, SCR_ADDR_SEL,
- C_FLAG_SEL, C_LD, C_SET, C_CLR, SHAD_C_LD,Z_FLAG_SEL,
- Z_LD, Z_SET, Z_CLR, SHAD_Z_LD, I_SET, I_CLR, IO_OE);
- --register instantiation
- reg1 : RegisterFile port map (RF_WR_DATA, SX, SY,
- IR(12 downto 8), IR(7 downto 3), RF_OE, RF_WR, CLK);
- --muxALU instantiation
- mx21 : muxQ21 port map (REG_IMMED_SEL, SY, IR(7 downto 0), B);
- --ALU instantiation
- Arthlu1 : alu1 port map (SX, B, C_FLAG, ALU_SEL, SUM, C_OUT, Z_OUT);
- --muxRF instantiation
- mx42 : muxQ417 port map (RF_WR_SEL, SUM, MULTI_BUS(7 downto 0), UNUSED, IN_PORT,
- RF_WR_DATA);
- --FlagRegC
- FlagC : FlagReg port map (C_OUT, C_LD, C_SET, C_CLR, CLK, C_FLAG);
- --FlagRegZ
- FlagZ : FlagReg port map (Z_OUT, Z_LD, Z_SET, Z_CLR, CLK, Z_FLAG);
- MULTI_BUS(7 downto 0) <= SX;
- PORT_ID <= IR(7 downto 0);
- OUT_PORT <= MULTI_BUS(7 downto 0);
- end behavioral;
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