import migen.fhdl.verilog
import migen.bus.wishbone
import milkymist.lm32

cpu = milkymist.lm32.Inst()
sharedbus = migen.bus.wishbone.Master()
arbiter = migen.bus.wishbone.Arbiter([cpu.ibus, cpu.dbus], sharedbus)
frag = cpu.GetFragment() + arbiter.GetFragment()
print(migen.fhdl.verilog.Convert(frag))