SHARE
TWEET

Untitled

a guest Dec 8th, 2011 23 Never
  1. import migen.fhdl.verilog
  2. import migen.bus.wishbone
  3. import milkymist.lm32
  4.  
  5. cpu = milkymist.lm32.Inst()
  6. sharedbus = migen.bus.wishbone.Master()
  7. arbiter = migen.bus.wishbone.Arbiter([cpu.ibus, cpu.dbus], sharedbus)
  8. frag = cpu.GetFragment() + arbiter.GetFragment()
  9. print(migen.fhdl.verilog.Convert(frag))
  10.  
  11.  
RAW Paste Data
Top