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Nov 24th, 2014
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VHDL 0.57 KB | None | 0 0
  1. entity F1 is
  2.  Port ( x1 : in STD_LOGIC;
  3.  x2 : in STD_LOGIC;
  4.  x3 : in STD_LOGIC;
  5.  y : out STD_LOGIC);
  6. end F1;
  7. architecture DMUX_NAND of F1 is
  8. component Nand3 is
  9.  Port ( a : in STD_LOGIC;
  10.  b : in STD_LOGIC;
  11.  c : in STD_LOGIC;
  12.  z : out STD_LOGIC);
  13. end component Nand3;
  14. component DMUX3 is
  15.  Port ( I : in STD_LOGIC;
  16.  A : in STD_LOGIC_VECTOR (2 downto 0);
  17.  nO : out STD_LOGIC_VECTOR (7 downto 0));
  18. end component DMUX3;
  19. signal nV :STD_LOGIC_VECTOR (7 downto 0);
  20. begin
  21. b1: DMUX3 port map('1', x1&x2&x3, nV);
  22. b2: Nand3 port map(nV(0), nV(6), nV(7), y);
  23. end DMUX_NAND;
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