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- entity F1 is
- Port ( x1 : in STD_LOGIC;
- x2 : in STD_LOGIC;
- x3 : in STD_LOGIC;
- y : out STD_LOGIC);
- end F1;
- architecture DMUX_NAND of F1 is
- component Nand3 is
- Port ( a : in STD_LOGIC;
- b : in STD_LOGIC;
- c : in STD_LOGIC;
- z : out STD_LOGIC);
- end component Nand3;
- component DMUX3 is
- Port ( I : in STD_LOGIC;
- A : in STD_LOGIC_VECTOR (2 downto 0);
- nO : out STD_LOGIC_VECTOR (7 downto 0));
- end component DMUX3;
- signal nV :STD_LOGIC_VECTOR (7 downto 0);
- begin
- b1: DMUX3 port map('1', x1&x2&x3, nV);
- b2: Nand3 port map(nV(0), nV(6), nV(7), y);
- end DMUX_NAND;
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