`timescale 1ns / 1ps

module testcounter(
    input wire clk,
    input wire resetn,
    input wire [31:0] num_to_count,
    output reg [7:0] output_signal
    );

    reg [31:0] counter;
    reg [7:0] output_drive;
    initial begin
        counter = 0;
    end

    initial begin
        output_drive = 0;
    end

    always@(negedge resetn) begin
        counter <= 0;
    end

    always@(posedge clk) begin
        if (counter == num_to_count) begin
            counter <= 0;
            output_drive <= output_drive ^ 8'hff;
        end
        else begin
            counter <= counter + 1;
        end
        output_signal <= output_drive;
    end



endmodule

module testcounter_testbench(

    );
    reg clk;
    reg resetn;
    reg [31:0] num_to_count;
    wire [7:0] output_signal;

    initial begin
        clk = 0;
        forever #1 clk = ~clk;
    end

    initial begin
        num_to_count = 20;
    end

    initial begin
        #7 resetn = 1;
        #35 resetn = 0;
    end

    testcounter A1(.clk(clk),.resetn(resetn),.num_to_count(num_to_count),.output_signal(output_signal));
endmodule