//My regMod:
module regMod(clk, data, out, notOut);
   input clk, data;
   output out, notOut;
   wire outTopAnd, outBottomAnd;
   wire outTopOr, outBottomOr;
   wire notData;
   not(notData, data);

   and(outTopAnd, data, clk);
   and(outBottomAnd, notData, clk);

   nor(outTopOr, outTopAnd, outBottomOr);
   nor(outBottomOr, outBottomAnd, outTopOr);
   assign notOut = outTopOr;
   assign out = outBottomOr;
endmodule

//This module was provided.
module ClockMod(clk);
   output clk;
   reg A;

   assign clk = A;
   initial A = 0;
   always begin
      #1 A = 1;
      #1 A = 0;
   end
endmodule


module CounterMod(clk, rst, q1, q0);
   input clk, rst;
   output q1, q0;//2 bit, 4 possible states.

   //Wire and register names
   wire registerOneData, registerTwoData;
   wire notRST, clkWire;

   wire notRegisterOneData, notRegisterTwoData;
   wire andOneOut, andTwoOut, andThreeOut, andFourOut;
   wire o1,o2,o3,o4;
   wire orOut1, orOut2;
   reg t1, t0;

   //t1 and t0 are the inputs looping back in.
   regMod regOne(clk, t1, registerOneData, notRegisterOneData);//s1
   regMod regTwo(clk, t0, registerTwoData, notRegisterTwoData);//s0

   //NOT the rst line
   not(notRST, rst);

//Set up AND gate lattice
   and(o1, notRST, notRegisterOneData);
   and(andOneOut, o1, registerTwoData);

   and(o2, notRST, registerOneData);

   and(andTwoOut, o2, notRegisterTwoData);

   and(o3, notRST, notRegisterOneData);
   and(andThreeOut, o3, notRegisterTwoData);

   and(o4, notRST, registerOneData);
   and(andFourOut, o4, notRegisterTwoData);

//Set up OR gate lattice
   or(orOut1, andOneOut, andTwoOut);
   or(orOut2, andThreeOut, andFourOut);
   assign q1 = orOut1;
   assign q0 = orOut2;

always@(negedge clk) begin
   t1 = q1;
   t0 = q0;

end
endmodule

module TestMod;
   reg rst;
   initial begin
      rst = 1;
      #1 rst = 0;
   end
   wire tyme, clk, q1, q0;

   ClockMod my_clock(clk);
   CounterMod my_counter(clk, rst, q1, q0);

   initial begin
      $display("Time  clk  rst   q1    q0");
      $display("-----------------------------------------");
    $monitor("%3d   %b   %b    %b    %b", $time, clk, rst, q1, q0);
   end

   initial #16 $finish;
endmodule