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- .title AND gate simulation
- A1 [1 2] 3 and
- .model and d_and(rise_delay=0.1ps fall_delay=0.2ps)
- * now test it
- Asource [1 2] d_source_model
- .model d_source_model d_source(input_file="2bit_input_for_AND")
- .tran 1ns 50ns
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