McASP PRU mode and ALSA mode register comparision

p. 175 ARM Cortex-A8 Memory Map
p. 178 L4_PER Peripheral Memory Map
p. 1206 Clock Module Registers (CM_PER Registers)
p. 1211 CM_PER_L3_CLKSTCTRL Register (Offset = 0xC) -
p. 1219 CM_PER_MCASP0_CLKCTRL Register (Offset = 0x34) - manages the MCASP0 clocks.

##### Memory Addresses of Registers #####
McASP0 CFG Register: 0x4803_8000 - 0x4803_9FFF
McASP1 CFG Register: 0x4803_C000 - 0x4803_DFFF
CM_PER Register: 0x44E0_0000 - 0x44E0_03FF

##### Specific Registers #####
CM_PER_L3_CLKSTCTRL Register Offset: 0xC
CM_PER_MCASP0_CLKCTRL Register Offset: 0x34
McASP GBLCTL Register Offset: 0x44

##### Specific Bits #####
CLKACTIVITY_MCASP_GCLK Bit: 7 (read only, 0x1 = active)
McASP0 IDLEST Bit: 17-16 (read only, 0x0 = Module fully functional)
McASP0 MODULEMODE Bit: 1-0 (r/w, 0x2 = Enable)

##### Commands #####
/* Get CM_PER_L3_CLKSTCTRL Register. Bit 7 = state of the MCASP_GCLK clock in the domain */
./devmem2 0x44E0000C w //0x56 = 1010110 => McASP_GCLK not active

/* Get CM_PER_MCASP0_CLKCTRL Register */
./devmem2 0x44E00034 w //0x30000 => IDLEST = fully functional, MODULEMODE = Disabled

/* Set CM_PER_MCASP0_CLKCTRL MODULEMODE bit (enable McASP interface and functional clock) */
./devmem2 0x44E00034 w 0x30002 //readback: 0x10002 => Module enabled => Avoids bus error when reading McASP cfg registers

####### McASP config registers (when in infinite loop (transmit buffer is written and full)) #######
DAVINCI_MCASP_TXFMCTL_REG 		Offset: 0xAC, Address: 0x480380AC
DAVINCI_MCASP_RXFMCTL_REG		Offset: 0x6C, Address: 0x4803806C
DAVINCI_MCASP_TXFMT_REG 		Offset: 0xA8, Address: 0x480380A8
DAVINCI_MCASP_RXFMT_REG 		Offset: 0x68, Address: 0x48038068
DAVINCI_MCASP_ACLKXCTL_REG 		Offset: 0xB0, Address: 0x480380B0
DAVINCI_MCASP_ACLKRCTL_REG 		Offset: 0x70, Address: 0x48038070
DAVINCI_MCASP_AHCLKXCTL_REG 	Offset: 0xB4, Address: 0x480380B4
DAVINCI_MCASP_AHCLKRCTL_REG 	Offset: 0x74, Address: 0x48038074
DAVINCI_MCASP_PDIR_REG 			Offset: 0x14, Address: 0x48038014
DAVINCI_MCASP_RXMASK_REG 		Offset: 0x64, Address: 0x48038064
DAVINCI_MCASP_TXMASK_REG 		Offset: 0xA4, Address: 0x480380A4
DAVINCI_MCASP_RXTDM_REG 		Offset: 0x78, Address: 0x48038078
DAVINCI_MCASP_TXTDM_REG 		Offset: 0xB8, Address: 0x480380B8

####### Register dump of McASP config registers in PRU mode 4.4 kernel #######
DAVINCI_MCASP_TXFMCTL_REG:		0x100
DAVINCI_MCASP_RXFMCTL_REG		0x100
DAVINCI_MCASP_TXFMT_REG 		0x807C
DAVINCI_MCASP_RXFMT_REG 		0x807C
DAVINCI_MCASP_ACLKXCTL_REG 		0x0
DAVINCI_MCASP_ACLKRCTL_REG 		0x80
DAVINCI_MCASP_AHCLKXCTL_REG 	0x8001
DAVINCI_MCASP_AHCLKRCTL_REG 	0x8001
DAVINCI_MCASP_PDIR_REG			0x8000004
DAVINCI_MCASP_RXMASK_REG 		0xFFFF
DAVINCI_MCASP_TXMASK_REG 		0xFFFF
DAVINCI_MCASP_RXTDM_REG 		0x3
DAVINCI_MCASP_TXTDM_REG 		0x3

####### Register dump of McASP config registers in PRU mode 3.8 kernel #######
DAVINCI_MCASP_TXFMCTL_REG:		0x0
DAVINCI_MCASP_RXFMCTL_REG		0x0
DAVINCI_MCASP_TXFMT_REG 		0x0
DAVINCI_MCASP_RXFMT_REG 		0x0
DAVINCI_MCASP_ACLKXCTL_REG 		0x60
DAVINCI_MCASP_ACLKRCTL_REG 		0x20
DAVINCI_MCASP_AHCLKXCTL_REG 	0x8000
DAVINCI_MCASP_AHCLKRCTL_REG 	0x8000
DAVINCI_MCASP_PDIR_REG			0x0
DAVINCI_MCASP_RXMASK_REG 		0x0
DAVINCI_MCASP_TXMASK_REG 		0x0
DAVINCI_MCASP_RXTDM_REG 		0x0
DAVINCI_MCASP_TXTDM_REG 		0x0

####### Register dump of McASP config registers in ALSA mode (BB-BONE-AUDI-02 overlay) #######
DAVINCI_MCASP_TXFMCTL_REG		0x100
DAVINCI_MCASP_RXFMCTL_REG		0x0
DAVINCI_MCASP_TXFMT_REG 		0x8074
DAVINCI_MCASP_RXFMT_REG 		0x70
DAVINCI_MCASP_ACLKXCTL_REG 		0x180040
DAVINCI_MCASP_ACLKRCTL_REG 		0x180000
DAVINCI_MCASP_AHCLKXCTL_REG 	0x188000
DAVINCI_MCASP_AHCLKRCTL_REG 	0x188000
DAVINCI_MCASP_PDIR_REG			0x4
DAVINCI_MCASP_RXMASK_REG 		0xFFFF
DAVINCI_MCASP_TXMASK_REG 		0xFFFF
DAVINCI_MCASP_RXTDM_REG 		0x0
DAVINCI_MCASP_TXTDM_REG 		0x3