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  1. #include <stdint.h>
  2. void error_led(void);
  3. void twiStart(void);
  4. void twiWriteByte(uint8_t DATA);
  5. void wrReg(uint8_t reg,uint8_t dat);
  6. uint8_t rdReg(uint8_t reg);
  7. void ov7670_store_cmatrix(void);
  8. void hueSatMatrix(int hue,int sat);
  9. #define camAddr_WR 0x42
  10. #define camAddr_RD 0x43
  11. /* Registers */
  12. #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
  13. #define REG_BLUE 0x01 /* blue gain */
  14. #define REG_RED 0x02 /* red gain */
  15. #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
  16. #define REG_COM1 0x04 /* Control 1 */
  17. #define COM1_CCIR656 0x40 /* CCIR656 enable */
  18. #define REG_BAVE 0x05 /* U/B Average level */
  19. #define REG_GbAVE 0x06 /* Y/Gb Average level */
  20. #define REG_AECHH 0x07 /* AEC MS 5 bits */
  21. #define REG_RAVE 0x08 /* V/R Average level */
  22. #define REG_COM2 0x09 /* Control 2 */
  23. #define COM2_SSLEEP 0x10 /* Soft sleep mode */
  24. #define REG_PID 0x0a /* Product ID MSB */
  25. #define REG_VER 0x0b /* Product ID LSB */
  26. #define REG_COM3 0x0c /* Control 3 */
  27. #define COM3_SWAP 0x40 /* Byte swap */
  28. #define COM3_SCALEEN 0x08 /* Enable scaling */
  29. #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
  30. #define REG_COM4 0x0d /* Control 4 */
  31. #define REG_COM5 0x0e /* All "reserved" */
  32. #define REG_COM6 0x0f /* Control 6 */
  33. #define REG_AECH 0x10 /* More bits of AEC value */
  34. #define REG_CLKRC 0x11 /* Clocl control */
  35. #define CLK_EXT 0x40 /* Use external clock directly */
  36. #define CLK_SCALE 0x3f /* Mask for internal clock scale */
  37. #define REG_COM7 0x12 /* Control 7 */
  38. #define COM7_RESET 0x80 /* Register reset */
  39. #define COM7_FMT_MASK 0x38
  40. #define COM7_FMT_VGA 0x00
  41. #define COM7_FMT_CIF 0x20 /* CIF format */
  42. #define COM7_FMT_QVGA 0x10 /* QVGA format */
  43. #define COM7_FMT_QCIF 0x08 /* QCIF format */
  44. #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
  45. #define COM7_YUV 0x00 /* YUV */
  46. #define COM7_BAYER 0x01 /* Bayer format */
  47. #define COM7_PBAYER 0x05 /* "Processed bayer" */
  48. #define REG_COM8 0x13 /* Control 8 */
  49. #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
  50. #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
  51. #define COM8_BFILT 0x20 /* Band filter enable */
  52. #define COM8_AGC 0x04 /* Auto gain enable */
  53. #define COM8_AWB 0x02 /* White balance enable */
  54. #define COM8_AEC 0x01 /* Auto exposure enable */
  55. #define REG_COM9 0x14 /* Control 9 - gain ceiling */
  56. #define REG_COM10 0x15 /* Control 10 */
  57. #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
  58. #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
  59. #define COM10_HREF_REV 0x08 /* Reverse HREF */
  60. #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
  61. #define COM10_VS_NEG 0x02 /* VSYNC negative */
  62. #define COM10_HS_NEG 0x01 /* HSYNC negative */
  63. #define REG_HSTART 0x17 /* Horiz start high bits */
  64. #define REG_HSTOP 0x18 /* Horiz stop high bits */
  65. #define REG_VSTART 0x19 /* Vert start high bits */
  66. #define REG_VSTOP 0x1a /* Vert stop high bits */
  67. #define REG_PSHFT 0x1b /* Pixel delay after HREF */
  68. #define REG_MIDH 0x1c /* Manuf. ID high */
  69. #define REG_MIDL 0x1d /* Manuf. ID low */
  70. #define REG_MVFP 0x1e /* Mirror / vflip */
  71. #define MVFP_MIRROR 0x20 /* Mirror image */
  72. #define MVFP_FLIP 0x10 /* Vertical flip */
  73.  
  74. #define REG_AEW 0x24 /* AGC upper limit */
  75. #define REG_AEB 0x25 /* AGC lower limit */
  76. #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
  77. #define REG_HSYST 0x30 /* HSYNC rising edge delay */
  78. #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
  79. #define REG_HREF 0x32 /* HREF pieces */
  80. #define REG_TSLB 0x3a /* lots of stuff */
  81. #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
  82. #define REG_COM11 0x3b /* Control 11 */
  83. #define COM11_NIGHT 0x80 /* NIght mode enable */
  84. #define COM11_NMFR 0x60 /* Two bit NM frame rate */
  85. #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
  86. #define COM11_50HZ 0x08 /* Manual 50Hz select */
  87. #define COM11_EXP 0x02
  88. #define REG_COM12 0x3c /* Control 12 */
  89. #define COM12_HREF 0x80 /* HREF always */
  90. #define REG_COM13 0x3d /* Control 13 */
  91. #define COM13_GAMMA 0x80 /* Gamma enable */
  92. #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
  93. #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
  94. #define REG_COM14 0x3e /* Control 14 */
  95. #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
  96. #define REG_EDGE 0x3f /* Edge enhancement factor */
  97. #define REG_COM15 0x40 /* Control 15 */
  98. #define COM15_R10F0 0x00 /* Data range 10 to F0 */
  99. #define COM15_R01FE 0x80 /* 01 to FE */
  100. #define COM15_R00FF 0xc0 /* 00 to FF */
  101. #define COM15_RGB565 0x10 /* RGB565 output */
  102. #define COM15_RGB555 0x30 /* RGB555 output */
  103. #define REG_COM16 0x41 /* Control 16 */
  104. #define COM16_AWBGAIN 0x08 /* AWB gain enable */
  105. #define REG_COM17 0x42 /* Control 17 */
  106. #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
  107. #define COM17_CBAR 0x08 /* DSP Color bar */
  108.  
  109. /*
  110. * This matrix defines how the colors are generated, must be
  111. * tweaked to adjust hue and saturation.
  112. *
  113. * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
  114. *
  115. * They are nine-bit signed quantities, with the sign bit
  116. * stored in 0x58. Sign for v-red is bit 0, and up from there.
  117. */
  118. #define REG_CMATRIX_BASE 0x4f
  119. #define CMATRIX_LEN 6
  120. #define REG_CMATRIX_SIGN 0x58
  121.  
  122.  
  123. #define REG_BRIGHT 0x55 /* Brightness */
  124. #define REG_CONTRAS 0x56 /* Contrast control */
  125.  
  126. #define REG_GFIX 0x69 /* Fix gain control */
  127.  
  128. #define REG_REG76 0x76 /* OV's name */
  129. #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
  130. #define R76_WHTPCOR 0x40 /* White pixel correction enable */
  131.  
  132. #define REG_RGB444 0x8c /* RGB 444 control */
  133. #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
  134. #define R444_RGBX 0x01 /* Empty nibble at end */
  135.  
  136. #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
  137. #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
  138.  
  139. #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
  140. #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
  141. #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
  142. #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
  143. #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
  144. #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
  145. #define REG_BD60MAX 0xab /* 60hz banding step limit */
  146.  
  147.  
  148. #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
  149. #define REG_BLUE 0x01 /* blue gain */
  150. #define REG_RED 0x02 /* red gain */
  151. #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
  152. #define REG_COM1 0x04 /* Control 1 */
  153. #define COM1_CCIR656 0x40 /* CCIR656 enable */
  154. #define REG_BAVE 0x05 /* U/B Average level */
  155. #define REG_GbAVE 0x06 /* Y/Gb Average level */
  156. #define REG_AECHH 0x07 /* AEC MS 5 bits */
  157. #define REG_RAVE 0x08 /* V/R Average level */
  158. #define REG_COM2 0x09 /* Control 2 */
  159. #define COM2_SSLEEP 0x10 /* Soft sleep mode */
  160. #define REG_PID 0x0a /* Product ID MSB */
  161. #define REG_VER 0x0b /* Product ID LSB */
  162. #define REG_COM3 0x0c /* Control 3 */
  163. #define COM3_SWAP 0x40 /* Byte swap */
  164. #define COM3_SCALEEN 0x08 /* Enable scaling */
  165. #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
  166. #define REG_COM4 0x0d /* Control 4 */
  167. #define REG_COM5 0x0e /* All "reserved" */
  168. #define REG_COM6 0x0f /* Control 6 */
  169. #define REG_AECH 0x10 /* More bits of AEC value */
  170. #define REG_CLKRC 0x11 /* Clocl control */
  171. #define CLK_EXT 0x40 /* Use external clock directly */
  172. #define CLK_SCALE 0x3f /* Mask for internal clock scale */
  173. #define REG_COM7 0x12 /* Control 7 */
  174. #define COM7_RESET 0x80 /* Register reset */
  175. #define COM7_FMT_MASK 0x38
  176. #define COM7_FMT_VGA 0x00
  177. #define COM7_FMT_CIF 0x20 /* CIF format */
  178. #define COM7_FMT_QVGA 0x10 /* QVGA format */
  179. #define COM7_FMT_QCIF 0x08 /* QCIF format */
  180. #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
  181. #define COM7_YUV 0x00 /* YUV */
  182. #define COM7_BAYER 0x01 /* Bayer format */
  183. #define COM7_PBAYER 0x05 /* "Processed bayer" */
  184. #define REG_COM8 0x13 /* Control 8 */
  185. #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
  186. #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
  187. #define COM8_BFILT 0x20 /* Band filter enable */
  188. #define COM8_AGC 0x04 /* Auto gain enable */
  189. #define COM8_AWB 0x02 /* White balance enable */
  190. #define COM8_AEC 0x01 /* Auto exposure enable */
  191. #define REG_COM9 0x14 /* Control 9 - gain ceiling */
  192. #define REG_COM10 0x15 /* Control 10 */
  193. #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
  194. #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
  195. #define COM10_HREF_REV 0x08 /* Reverse HREF */
  196. #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
  197. #define COM10_VS_NEG 0x02 /* VSYNC negative */
  198. #define COM10_HS_NEG 0x01 /* HSYNC negative */
  199. #define REG_HSTART 0x17 /* Horiz start high bits */
  200. #define REG_HSTOP 0x18 /* Horiz stop high bits */
  201. #define REG_VSTART 0x19 /* Vert start high bits */
  202. #define REG_VSTOP 0x1a /* Vert stop high bits */
  203. #define REG_PSHFT 0x1b /* Pixel delay after HREF */
  204. #define REG_MIDH 0x1c /* Manuf. ID high */
  205. #define REG_MIDL 0x1d /* Manuf. ID low */
  206. #define REG_MVFP 0x1e /* Mirror / vflip */
  207. #define MVFP_MIRROR 0x20 /* Mirror image */
  208. #define MVFP_FLIP 0x10 /* Vertical flip */
  209. #define REG_AEW 0x24 /* AGC upper limit */
  210. #define REG_AEB 0x25 /* AGC lower limit */
  211. #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
  212. #define REG_HSYST 0x30 /* HSYNC rising edge delay */
  213. #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
  214. #define REG_HREF 0x32 /* HREF pieces */
  215. #define REG_TSLB 0x3a /* lots of stuff */
  216. #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
  217. #define REG_COM11 0x3b /* Control 11 */
  218. #define COM11_NIGHT 0x80 /* NIght mode enable */
  219. #define COM11_NMFR 0x60 /* Two bit NM frame rate */
  220. #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
  221. #define COM11_50HZ 0x08 /* Manual 50Hz select */
  222. #define COM11_EXP 0x02
  223. #define REG_COM12 0x3c /* Control 12 */
  224. #define COM12_HREF 0x80 /* HREF always */
  225. #define REG_COM13 0x3d /* Control 13 */
  226. #define COM13_GAMMA 0x80 /* Gamma enable */
  227. #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
  228. #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
  229. #define REG_COM14 0x3e /* Control 14 */
  230. #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
  231. #define REG_EDGE 0x3f /* Edge enhancement factor */
  232. #define REG_COM15 0x40 /* Control 15 */
  233. #define COM15_R10F0 0x00 /* Data range 10 to F0 */
  234. #define COM15_R01FE 0x80 /* 01 to FE */
  235. #define COM15_R00FF 0xc0 /* 00 to FF */
  236. #define COM15_RGB565 0x10 /* RGB565 output */
  237. #define COM15_RGB555 0x30 /* RGB555 output */
  238. #define REG_COM16 0x41 /* Control 16 */
  239. #define COM16_AWBGAIN 0x08 /* AWB gain enable */
  240. #define REG_COM17 0x42 /* Control 17 */
  241. #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
  242. #define COM17_CBAR 0x08 /* DSP Color bar */
  243.  
  244. #define CMATRIX_LEN 6
  245. #define REG_BRIGHT 0x55 /* Brightness */
  246. #define REG_REG76 0x76 /* OV's name */
  247. #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
  248. #define R76_WHTPCOR 0x40 /* White pixel correction enable */
  249. #define REG_RGB444 0x8c /* RGB 444 control */
  250. #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
  251. #define R444_RGBX 0x01 /* Empty nibble at end */
  252. #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
  253. #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
  254. #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
  255. #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
  256. #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
  257. #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
  258. #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
  259. #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
  260. #define REG_BD60MAX 0xab /* 60hz banding step limit */
  261.  
  262. #define MTX1 0x4f /* Matrix Coefficient 1 */
  263. #define MTX2 0x50 /* Matrix Coefficient 2 */
  264. #define MTX3 0x51 /* Matrix Coefficient 3 */
  265. #define MTX4 0x52 /* Matrix Coefficient 4 */
  266. #define MTX5 0x53 /* Matrix Coefficient 5 */
  267. #define MTX6 0x54 /* Matrix Coefficient 6 */
  268. #define REG_CONTRAS 0x56 /* Contrast control */
  269. #define MTXS 0x58 /* Matrix Coefficient Sign */
  270. #define AWBC7 0x59 /* AWB Control 7 */
  271. #define AWBC8 0x5a /* AWB Control 8 */
  272. #define AWBC9 0x5b /* AWB Control 9 */
  273. #define AWBC10 0x5c /* AWB Control 10 */
  274. #define AWBC11 0x5d /* AWB Control 11 */
  275. #define AWBC12 0x5e /* AWB Control 12 */
  276. #define REG_GFIX 0x69 /* Fix gain control */
  277. #define GGAIN 0x6a /* G Channel AWB Gain */
  278. #define DBLV 0x6b
  279. #define AWBCTR3 0x6c /* AWB Control 3 */
  280. #define AWBCTR2 0x6d /* AWB Control 2 */
  281. #define AWBCTR1 0x6e /* AWB Control 1 */
  282. #define AWBCTR0 0x6f /* AWB Control 0 */
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