include "lpm_shiftreg.inc";
include "lpm_counter.inc";

SUBDESIGN uart
(
	clock, in	:	input;
	out[7..0]	:	output;
)

VARIABLE
	shifter: lpm_shiftreg with (
				lpm_width=8,
				lpm_direction="left"
			 );

	divider[3..1]: dff;

	outer: lpm_shiftreg with
		(lpm_width=8, lpm_direction="left");

	counter: lpm_counter with (
				lpm_width=4,
				lpm_direction="up"
			 );

	state: MACHINE with
		   STATES (wait, start, read, finish);

BEGIN

	TABLE
		shifter.q[6..2]	=> outer.shiftin;
		b"00000"	=>	GND;
		b"00001"	=>	GND;
		b"00010"	=>	GND;
		b"00011"	=>	GND;
		b"00100"	=>	GND;
		b"00101"	=>	GND;
		b"00110"	=>	GND;
		b"00111"	=>	VCC;
		b"01000"	=>	GND;
		b"01001"	=>	GND;
		b"01010"	=>	GND;
		b"01011"	=>	VCC;
		b"01100"	=>	GND;
		b"01101"	=>	VCC;
		b"01110"	=>	VCC;
		b"01111"	=>	VCC;
		b"10000"	=>	GND;
		b"10001"	=>	GND;
		b"10010"	=>	GND;
		b"10011"	=>	VCC;
		b"10100"	=>	GND;
		b"10101"	=>	VCC;
		b"10110"	=>	VCC;
		b"10111"	=>	VCC;
		b"11000"	=>	GND;
		b"11001"	=>	VCC;
		b"11010"	=>	VCC;
		b"11011"	=>	VCC;
		b"11100"	=>	VCC;
		b"11101"	=>	VCC;
		b"11110"	=>	VCC;
		b"11111"	=>	VCC;
	END TABLE;

	divider[].d = !divider[].q;
	divider[1].clk = clock;
	divider[3..2].clk = divider[2..1].q;

	shifter.clock = !clock;
	shifter.shiftin = in;

	counter.clock = divider[3].q;
	state.clk = divider[3].q;

	CASE state IS
		WHEN wait =>
			IF (in == VCC) THEN
				state = start;
			END IF;

			counter.cnt_en = GND;
			counter.sclr = GND;
			shifter.sclr = VCC;

		WHEN start =>
			counter.cnt_en = VCC;
			counter.sclr = GND;
			state = read;
			shifter.sclr = VCC;

		WHEN read =>
			counter.cnt_en = VCC;

			IF (counter.q[] == 8) THEN
				counter.sclr = VCC;
				state = finish;
			END IF;

			shifter.sclr = GND;

		WHEN finish =>
			counter.cnt_en = VCC;

			IF (counter.q[] == 2) THEN
				counter.sclr = VCC;
				state = wait;
			END IF;

			shifter.sclr = VCC;
	END CASE;

	outer.clock = divider[3].q;
	out[7..0]=outer.q[7..0];

END;