uc3_a3_xplained.h

#ifndef UC3_A3_XPLAINED_H_
#define UC3_A3_XPLAINED_H_

#include "compiler.h"

#ifdef __AVR32_ABI_COMPILER__
#  include "led.h"
#endif


#ifdef __cplusplus
extern "C" {
#endif



/* RCOsc frequency: Hz. */
#define FRCOSC                      (AVR32_PM_RCOSC_FREQUENCY)

/** Osc32 frequency (Hz.) and startup time (RCOsc periods). */
#define FOSC32                      (32768)
#define OSC32_STARTUP               (AVR32_PM_OSCCTRL32_STARTUP_8192_RCOSC)

#define BOARD_OSC32_IS_XTAL         true
#define BOARD_OSC32_HZ              FOSC32
#define BOARD_OSC32_STARTUP_US      (570000)

/** Osc frequency (Hz.) and startup time (RCOsc periods). */
#define FOSC0                       (12000000)
#define OSC0_STARTUP                (AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC)

#define BOARD_OSC0_IS_XTAL          true
#define BOARD_OSC0_HZ               FOSC0
#define BOARD_OSC0_STARTUP_US       (18000)
/** @} */

/* \def Number of LEDs. */
#define LED_COUNT                   4

/* \name UC3-A3-Xplained LED to GPIO pin mappings.
 * @{
 */
#define LED0_GPIO                   (AVR32_PIN_PB03)
#define LED1_GPIO                   (AVR32_PIN_PX22)
#define LED2_GPIO                   (AVR32_PIN_PB02)
#define LED3_GPIO                   (AVR32_PIN_PB06)
/** @} */

/** \name GPIO Connections of Push Buttons
 * @{
 */
#define GPIO_PUSH_BUTTON_0          (AVR32_PIN_PB01)
#define GPIO_PUSH_BUTTON_0_PRESSED  (0)
/** @} */

/** \name SDRAM Definitions
 * @{
 */
/** Part header file of used SDRAM(s). */
#define SDRAM_PART_HDR              "mt48lc16m16a2tg7e/mt48lc16m16a2tg7e.h"

/** SDRAM(s) data bus width (always 16 bits on UC3) */
#define SDRAM_DBW                    16
/** @} */

/** \name USART connections to the UC3B board controller
 * @{
 */
#define USART                       (&AVR32_USART1)
#define USART_RXD_PIN               AVR32_USART1_RXD_0_0_PIN
#define USART_RXD_FUNCTION          AVR32_USART1_RXD_0_0_FUNCTION
#define USART_TXD_PIN               AVR32_USART1_TXD_0_0_PIN
#define USART_TXD_FUNCTION          AVR32_USART1_TXD_0_0_FUNCTION
#define USART_IRQ                   AVR32_USART1_IRQ
#define USART_IRQ_GROUP             AVR32_USART1_IRQ_GROUP
#define USART_SYSCLK                SYSCLK_USART1
/** @} */

/** \name TWI Master connections to GPIO
 *
 * \todo
 * The TWIM pins that are mapped here should correspond with the TWIM
 * interfaces selected in the conf_board.h file.  In addition, the
 * default values below map TWIM the pins on the Xplaned J1 block.
 * Modify the mappings or add appropriate conditional compilation as
 * needed.
 *
 * @{
 */
#define TWIMS0_TWD_PIN              AVR32_TWIMS0_TWD_0_0_PIN
#define TWIMS0_TWD_FUNCTION         AVR32_TWIMS0_TWD_0_0_FUNCTION
#define TWIMS0_TWCK_PIN             AVR32_TWIMS0_TWCK_0_0_PIN
#define TWIMS0_TWCK_FUNCTION        AVR32_TWIMS0_TWCK_0_0_FUNCTION
/** @} */



/** \name Header J1 SPI1
 * @{
 */
#define HeaderJ1_SPI                 (&AVR32_SPI1)
#define HeaderJ1_SPI_NPCS            0
#define HeaderJ1_SPI_SCK_PIN         AVR32_SPI1_SCK_0_0_PIN
#define HeaderJ1_SPI_SCK_FUNCTION    AVR32_SPI1_SCK_0_0_FUNCTION
#define HeaderJ1_SPI_MISO_PIN        AVR32_SPI1_MISO_0_0_PIN
#define HeaderJ1_SPI_MISO_FUNCTION   AVR32_SPI1_MISO_0_0_FUNCTION
#define HeaderJ1_SPI_MOSI_PIN        AVR32_SPI1_MOSI_0_0_PIN
#define HeaderJ1_SPI_MOSI_FUNCTION   AVR32_SPI1_MOSI_0_0_FUNCTION
#define HeaderJ1_SPI_NPCS0_PIN       AVR32_SPI1_NPCS_0_0_PIN        // Verwendeter NPCS auf SS-Pin
#define HeaderJ1_SPI_NPCS0_FUNCTION  AVR32_SPI1_NPCS_0_0_FUNCTION
#define HeaderJ1_SPI_NPCS1_PIN       AVR32_SPI1_NPCS_1_0_PIN
#define HeaderJ1_SPI_NPCS1_FUNCTION  AVR32_SPI1_NPCS_1_0_FUNCTION
#define HeaderJ1_SPI_NPCS2_PIN       AVR32_SPI1_NPCS_2_0_PIN
#define HeaderJ1_SPI_NPCS2_FUNCTION  AVR32_SPI1_NPCS_2_0_FUNCTION
#define HeaderJ1_SPI_NPCS3_PIN       AVR32_SPI1_NPCS_3_PIN
#define HeaderJ1_SPI_NPCS3_FUNCTION  AVR32_SPI1_NPCS_3_FUNCTION
/** @} */


/** Validate board support for the common sensor service. */
#define                             COMMON_SENSOR_PLATFORM

/** \name SPI Connections of the AT45DBX Data Flash Memory
 * @{
 */
// SPI 0 liegt auf Header J4
#define AT45DBX_SPI                 (&AVR32_SPI0)
#define AT45DBX_SPI_NPCS            1
#define AT45DBX_SPI_SCK_PIN         AVR32_SPI0_SCK_0_0_PIN
#define AT45DBX_SPI_SCK_FUNCTION    AVR32_SPI0_SCK_0_0_FUNCTION
#define AT45DBX_SPI_MISO_PIN        AVR32_SPI0_MISO_0_0_PIN
#define AT45DBX_SPI_MISO_FUNCTION   AVR32_SPI0_MISO_0_0_FUNCTION
#define AT45DBX_SPI_MOSI_PIN        AVR32_SPI0_MOSI_0_0_PIN
#define AT45DBX_SPI_MOSI_FUNCTION   AVR32_SPI0_MOSI_0_0_FUNCTION
#define AT45DBX_SPI_NPCS0_PIN       AVR32_SPI0_NPCS_1_0_PIN
#define AT45DBX_SPI_NPCS0_FUNCTION  AVR32_SPI0_NPCS_1_0_FUNCTION
/** @} */

/** @} */ // at32uc3a3_xpld_config group

#ifdef __cplusplus
}
#endif

#endif /* UC3_A3_XPLAINED_H_ */