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  1.  
  2. // constant definitions for overcurrent thresholds. Write these values to
  3. // register dSPIN_OCD_TH to set the level at which an overcurrent even occurs.
  4. #define dSPIN_OCD_TH_375mA 0x00
  5. #define dSPIN_OCD_TH_750mA 0x01
  6. #define dSPIN_OCD_TH_1125mA 0x02
  7. #define dSPIN_OCD_TH_1500mA 0x03
  8. #define dSPIN_OCD_TH_1875mA 0x04
  9. #define dSPIN_OCD_TH_2250mA 0x05
  10. #define dSPIN_OCD_TH_2625mA 0x06
  11. #define dSPIN_OCD_TH_3000mA 0x07
  12. #define dSPIN_OCD_TH_3375mA 0x08
  13. #define dSPIN_OCD_TH_3750mA 0x09
  14. #define dSPIN_OCD_TH_4125mA 0x0A
  15. #define dSPIN_OCD_TH_4500mA 0x0B
  16. #define dSPIN_OCD_TH_4875mA 0x0C
  17. #define dSPIN_OCD_TH_5250mA 0x0D
  18. #define dSPIN_OCD_TH_5625mA 0x0E
  19. #define dSPIN_OCD_TH_6000mA 0x0F
  20.  
  21. // STEP_MODE option values.
  22. // First comes the "microsteps per step" options...
  23. #define dSPIN_STEP_MODE_STEP_SEL 0x07 // Mask for these bits only.
  24. #define dSPIN_STEP_SEL_1 0x00
  25. #define dSPIN_STEP_SEL_1_2 0x01
  26. #define dSPIN_STEP_SEL_1_4 0x02
  27. #define dSPIN_STEP_SEL_1_8 0x03
  28. #define dSPIN_STEP_SEL_1_16 0x04
  29. #define dSPIN_STEP_SEL_1_32 0x05
  30. #define dSPIN_STEP_SEL_1_64 0x06
  31. #define dSPIN_STEP_SEL_1_128 0x07
  32.  
  33. // ...next, define the SYNC_EN bit. When set, the BUSYN pin will instead
  34. // output a clock related to the full-step frequency as defined by the
  35. // SYNC_SEL bits below.
  36. #define dSPIN_STEP_MODE_SYNC_EN 0x80 // Mask for this bit
  37. #define dSPIN_SYNC_EN 0x80
  38.  
  39. // ...last, define the SYNC_SEL modes. The clock output is defined by
  40. // the full-step frequency and the value in these bits- see the datasheet
  41. // for a matrix describing that relationship (page 46).
  42. #define dSPIN_STEP_MODE_SYNC_SEL 0x70
  43. #define dSPIN_SYNC_SEL_1_2 0x00
  44. #define dSPIN_SYNC_SEL_1 0x10
  45. #define dSPIN_SYNC_SEL_2 0x20
  46. #define dSPIN_SYNC_SEL_4 0x30
  47. #define dSPIN_SYNC_SEL_8 0x40
  48. #define dSPIN_SYNC_SEL_16 0x50
  49. #define dSPIN_SYNC_SEL_32 0x60
  50. #define dSPIN_SYNC_SEL_64 0x70
  51.  
  52. // Bit names for the ALARM_EN register.
  53. // Each of these bits defines one potential alarm condition.
  54. // When one of these conditions occurs and the respective bit in ALARM_EN is set,
  55. // the FLAG pin will go low. The register must be queried to determine which event
  56. // caused the alarm.
  57. #define dSPIN_ALARM_EN_OVERCURRENT 0x01
  58. #define dSPIN_ALARM_EN_THERMAL_SHUTDOWN 0x02
  59. #define dSPIN_ALARM_EN_THERMAL_WARNING 0x04
  60. #define dSPIN_ALARM_EN_UNDER_VOLTAGE 0x08
  61. #define dSPIN_ALARM_EN_STALL_DET_A 0x10
  62. #define dSPIN_ALARM_EN_STALL_DET_B 0x20
  63. #define dSPIN_ALARM_EN_SW_TURN_ON 0x40
  64. #define dSPIN_ALARM_EN_WRONG_NPERF_CMD 0x80
  65.  
  66. // CONFIG register renames.
  67.  
  68. // Oscillator options.
  69. // The dSPIN needs to know what the clock frequency is because it uses that for some
  70. // calculations during operation.
  71. #define dSPIN_CONFIG_OSC_SEL 0x000F // Mask for this bit field.
  72. #define dSPIN_CONFIG_INT_16MHZ 0x0000 // Internal 16MHz, no output
  73. #define dSPIN_CONFIG_INT_16MHZ_OSCOUT_2MHZ 0x0008 // Default; internal 16MHz, 2MHz output
  74. #define dSPIN_CONFIG_INT_16MHZ_OSCOUT_4MHZ 0x0009 // Internal 16MHz, 4MHz output
  75. #define dSPIN_CONFIG_INT_16MHZ_OSCOUT_8MHZ 0x000A // Internal 16MHz, 8MHz output
  76. #define dSPIN_CONFIG_INT_16MHZ_OSCOUT_16MHZ 0x000B // Internal 16MHz, 16MHz output
  77. #define dSPIN_CONFIG_EXT_8MHZ_XTAL_DRIVE 0x0004 // External 8MHz crystal
  78. #define dSPIN_CONFIG_EXT_16MHZ_XTAL_DRIVE 0x0005 // External 16MHz crystal
  79. #define dSPIN_CONFIG_EXT_24MHZ_XTAL_DRIVE 0x0006 // External 24MHz crystal
  80. #define dSPIN_CONFIG_EXT_32MHZ_XTAL_DRIVE 0x0007 // External 32MHz crystal
  81. #define dSPIN_CONFIG_EXT_8MHZ_OSCOUT_INVERT 0x000C // External 8MHz crystal, output inverted
  82. #define dSPIN_CONFIG_EXT_16MHZ_OSCOUT_INVERT 0x000D // External 16MHz crystal, output inverted
  83. #define dSPIN_CONFIG_EXT_24MHZ_OSCOUT_INVERT 0x000E // External 24MHz crystal, output inverted
  84. #define dSPIN_CONFIG_EXT_32MHZ_OSCOUT_INVERT 0x000F // External 32MHz crystal, output inverted
  85.  
  86. // Configure the functionality of the external switch input
  87. #define dSPIN_CONFIG_SW_MODE 0x0010 // Mask for this bit.
  88. #define dSPIN_CONFIG_SW_HARD_STOP 0x0000 // Default; hard stop motor on switch.
  89. #define dSPIN_CONFIG_SW_USER 0x0010 // Tie to the GoUntil and ReleaseSW
  90. // commands to provide jog function.
  91. // See page 25 of datasheet.
  92.  
  93. // Configure the motor voltage compensation mode (see page 34 of datasheet)
  94. #define dSPIN_CONFIG_EN_VSCOMP 0x0020 // Mask for this bit.
  95. #define dSPIN_CONFIG_VS_COMP_DISABLE 0x0000 // Disable motor voltage compensation.
  96. #define dSPIN_CONFIG_VS_COMP_ENABLE 0x0020 // Enable motor voltage compensation.
  97.  
  98. // Configure overcurrent detection event handling
  99. #define dSPIN_CONFIG_OC_SD 0x0080 // Mask for this bit.
  100. #define dSPIN_CONFIG_OC_SD_DISABLE 0x0000 // Bridges do NOT shutdown on OC detect
  101. #define dSPIN_CONFIG_OC_SD_ENABLE 0x0080 // Bridges shutdown on OC detect
  102.  
  103. // Configure the slew rate of the power bridge output
  104. #define dSPIN_CONFIG_POW_SR 0x0300 // Mask for this bit field.
  105. #define dSPIN_CONFIG_SR_180V_us 0x0000 // 180V/us
  106. #define dSPIN_CONFIG_SR_290V_us 0x0200 // 290V/us
  107. #define dSPIN_CONFIG_SR_530V_us 0x0300 // 530V/us
  108.  
  109. // Integer divisors for PWM sinewave generation
  110. // See page 32 of the datasheet for more information on this.
  111. #define dSPIN_CONFIG_F_PWM_DEC 0x1C00 // mask for this bit field
  112. #define dSPIN_CONFIG_PWM_MUL_0_625 (0x00)<<10
  113. #define dSPIN_CONFIG_PWM_MUL_0_75 (0x01)<<10
  114. #define dSPIN_CONFIG_PWM_MUL_0_875 (0x02)<<10
  115. #define dSPIN_CONFIG_PWM_MUL_1 (0x03)<<10
  116. #define dSPIN_CONFIG_PWM_MUL_1_25 (0x04)<<10
  117. #define dSPIN_CONFIG_PWM_MUL_1_5 (0x05)<<10
  118. #define dSPIN_CONFIG_PWM_MUL_1_75 (0x06)<<10
  119. #define dSPIN_CONFIG_PWM_MUL_2 (0x07)<<10
  120.  
  121. // Multiplier for the PWM sinewave frequency
  122. #define dSPIN_CONFIG_F_PWM_INT 0xE000 // mask for this bit field.
  123. #define dSPIN_CONFIG_PWM_DIV_1 (0x00)<<13
  124. #define dSPIN_CONFIG_PWM_DIV_2 (0x01)<<13
  125. #define dSPIN_CONFIG_PWM_DIV_3 (0x02)<<13
  126. #define dSPIN_CONFIG_PWM_DIV_4 (0x03)<<13
  127. #define dSPIN_CONFIG_PWM_DIV_5 (0x04)<<13
  128. #define dSPIN_CONFIG_PWM_DIV_6 (0x05)<<13
  129. #define dSPIN_CONFIG_PWM_DIV_7 (0x06)<<13
  130.  
  131. // Status register bit renames- read-only bits conferring information about the
  132. // device to the user.
  133. #define dSPIN_STATUS_HIZ 0x0001 // high when bridges are in HiZ mode
  134. #define dSPIN_STATUS_BUSY 0x0002 // mirrors BUSY pin
  135. #define dSPIN_STATUS_SW_F 0x0004 // low when switch open, high when closed
  136. #define dSPIN_STATUS_SW_EVN 0x0008 // active high, set on switch falling edge,
  137. // cleared by reading STATUS
  138. #define dSPIN_STATUS_DIR 0x0010 // Indicates current motor direction.
  139. // High is FWD, Low is REV.
  140. #define dSPIN_STATUS_NOTPERF_CMD 0x0080 // Last command not performed.
  141. #define dSPIN_STATUS_WRONG_CMD 0x0100 // Last command not valid.
  142. #define dSPIN_STATUS_UVLO 0x0200 // Undervoltage lockout is active
  143. #define dSPIN_STATUS_TH_WRN 0x0400 // Thermal warning
  144. #define dSPIN_STATUS_TH_SD 0x0800 // Thermal shutdown
  145. #define dSPIN_STATUS_OCD 0x1000 // Overcurrent detected
  146. #define dSPIN_STATUS_STEP_LOSS_A 0x2000 // Stall detected on A bridge
  147. #define dSPIN_STATUS_STEP_LOSS_B 0x4000 // Stall detected on B bridge
  148. #define dSPIN_STATUS_SCK_MOD 0x8000 // Step clock mode is active
  149.  
  150. // Status register motor status field
  151. #define dSPIN_STATUS_MOT_STATUS 0x0060 // field mask
  152. #define dSPIN_STATUS_MOT_STATUS_STOPPED (0x0000)<<13 // Motor stopped
  153. #define dSPIN_STATUS_MOT_STATUS_ACCELERATION (0x0001)<<13 // Motor accelerating
  154. #define dSPIN_STATUS_MOT_STATUS_DECELERATION (0x0002)<<13 // Motor decelerating
  155. #define dSPIN_STATUS_MOT_STATUS_CONST_SPD (0x0003)<<13 // Motor at constant speed
  156.  
  157. // Register address redefines.
  158. // See the dSPIN_Param_Handler() function for more info about these.
  159. #define dSPIN_ABS_POS 0x01
  160. #define dSPIN_EL_POS 0x02
  161. #define dSPIN_MARK 0x03
  162. #define dSPIN_SPEED 0x04
  163. #define dSPIN_ACC 0x05
  164. #define dSPIN_DEC 0x06
  165. #define dSPIN_MAX_SPEED 0x07
  166. #define dSPIN_MIN_SPEED 0x08
  167. #define dSPIN_FS_SPD 0x15
  168. #define dSPIN_KVAL_HOLD 0x09
  169. #define dSPIN_KVAL_RUN 0x0A
  170. #define dSPIN_KVAL_ACC 0x0B
  171. #define dSPIN_KVAL_DEC 0x0C
  172. #define dSPIN_INT_SPD 0x0D
  173. #define dSPIN_ST_SLP 0x0E
  174. #define dSPIN_FN_SLP_ACC 0x0F
  175. #define dSPIN_FN_SLP_DEC 0x10
  176. #define dSPIN_K_THERM 0x11
  177. #define dSPIN_ADC_OUT 0x12
  178. #define dSPIN_OCD_TH 0x13
  179. #define dSPIN_STALL_TH 0x14
  180. #define dSPIN_STEP_MODE 0x16
  181. #define dSPIN_ALARM_EN 0x17
  182. #define dSPIN_CONFIG 0x18
  183. #define dSPIN_STATUS 0x19
  184.  
  185. //dSPIN commands
  186. #define dSPIN_NOP 0x00
  187. #define dSPIN_SET_PARAM 0x00
  188. #define dSPIN_GET_PARAM 0x20
  189. #define dSPIN_RUN 0x50
  190. #define dSPIN_STEP_CLOCK 0x58
  191. #define dSPIN_MOVE 0x40
  192. #define dSPIN_GOTO 0x60
  193. #define dSPIN_GOTO_DIR 0x68
  194. #define dSPIN_GO_UNTIL 0x82
  195. #define dSPIN_RELEASE_SW 0x92
  196. #define dSPIN_GO_HOME 0x70
  197. #define dSPIN_GO_MARK 0x78
  198. #define dSPIN_RESET_POS 0xD8
  199. #define dSPIN_RESET_DEVICE 0xC0
  200. #define dSPIN_SOFT_STOP 0xB0
  201. #define dSPIN_HARD_STOP 0xB8
  202. #define dSPIN_SOFT_HIZ 0xA0
  203. #define dSPIN_HARD_HIZ 0xA8
  204. #define dSPIN_GET_STATUS 0xD0
  205.  
  206. /* dSPIN direction options */
  207. #define FWD 0x01
  208. #define REV 0x00
  209.  
  210. /* dSPIN action options */
  211. #define ACTION_RESET 0x00
  212. #define ACTION_COPY 0x01
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