`timescale 10us/1us
module clockcheck_tb();
  reg refclk_tb;
  reg clkin_tb;
  reg [31:0] freq_tb;

  clockcheck U0(.clkin(clkin_tb), .refclk(refclk_tb), .freq(freq_tb));

  	initial begin
		  refclk_tb = 0;
	 end
	 always
	   #2 refclk_tb = !refclk_tb;

	 initial begin
	   clkin_tb = 0;
	 end
	 always
	   #20 clkin_tb = !clkin_tb;

  initial begin
    $display("Frequencia = %d", freq_tb);
  end

endmodule

--------------------------------------------------------------------------------------------------------

# ** Error: (vsim-3053) C:/Users/Gabriel/Desktop/Faculdade/V-Semestre/Eletrônica-Digital/Eletrônica-Digital/Lista3/Clockcheck/clkcheck_tb.v(7): Illegal output or inout port connection for "port 'freq'".
#
#         Region: /clockcheck_tb/U0