counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity counter is
generic(n: integer := 4);

port( clock:      in std_logic;
      reset:      in std_logic;
      UpDownCount: in std_logic;
      Q:    out std_logic_vector(n-1 downto 0));
end counter;

architecture Behavioral of counter is
  --signal declaration
  signal temp : std_logic_vector(3 downto 0);

Begin
  Process(clock, reset, UpDownCount, temp) is
    Begin
      if reset = '1' then
        temp <= "0000";
      elsif (clock'event and clock = '1') then
        if(UpDownCount = '1') then
          if(temp = "1111") then
            temp <= "0000";
          else
            temp <= temp + "0001";
          end if;
        else
          if(temp = "0000") then
            temp <= "1111";
          else
            temp <= temp - "0001";
          end if;
        end if;
      end if;
    end process;

    Q <= temp;
  end Behavioral;