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Mar 27th, 2015
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VHDL 2.68 KB | None | 0 0
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.std_logic_unsigned.all;
  4.  
  5. entity PanelDisplay is
  6. port (clk : in std_logic;
  7. rst : in std_logic;
  8. hsync : out std_logic;
  9. vsync : out std_logic;
  10. red : out std_logic_vector(3 downto 0);
  11. green : out std_logic_vector(3 downto 0);
  12. blue : out std_logic_vector(3 downto 0));
  13. end PanelDisplay;
  14.  
  15. architecture main of PanelDisplay is
  16. signal hpos: integer range 0 to 800:=0;
  17. signal vpos: integer range 0 to 524:=0;
  18. signal Xpos: integer range 0 to 800:=0;
  19. signal Ypos: integer range 0 to 524:=0;
  20. signal temp: STD_LOGIC:='1';
  21. signal counter : integer range 0 to 1:=0;
  22. signal clk_out: STD_LOGIC:='1';
  23. begin
  24.  
  25.  
  26.      ---------------------
  27.     --  Frequency div  --
  28.     ---------------------
  29.  
  30. process (clk) begin
  31.         if rising_edge(clk) then
  32.             if (counter = 1) then
  33.                 temp <= NOT(temp);
  34.                 counter <= 0;
  35.             else
  36.                 counter <= counter + 1;
  37.             end if;
  38.         end if;
  39. clk_out<= temp;
  40. end process;
  41.  
  42.  
  43.  
  44. process (clk_out) begin
  45. if (rising_edge(clk_out)) then
  46.  
  47.      -------------------
  48.     --   HPOS, VPOS  --
  49.     -------------------
  50.     if (hpos<800) then
  51.         hpos <= hpos+1;
  52.     else
  53.         hpos<=0;
  54.         if (vpos<524)then
  55.             vpos<=vpos+1;
  56.         else
  57.             vpos<=0;
  58.         end if;
  59.     end if;
  60.    
  61.      ---------------------
  62.     --   HSYNC, VSYNC  --
  63.     ---------------------
  64.     if (hpos>16 and hpos<144) then
  65.         hsync<='0';
  66.     else
  67.         hsync<='1';
  68.     end if;
  69.    
  70.     if (vpos>10 and vpos<13) then
  71.         vsync<='0';
  72.     else
  73.         vsync<='1';
  74.     end if;
  75.    
  76.     -- Blanking period
  77.     if ((hpos>0 and hpos<160) or (vpos>0 and vpos<44)) then
  78.         red<=(others =>'0');
  79.         green<=(others =>'0');
  80.         blue<=(others =>'0');
  81.     end if;
  82.  
  83.  
  84.    
  85.    
  86.    
  87.  
  88.     Xpos<=405;
  89.     Ypos<=209;
  90.      ------------------
  91.     --    Block #1  --
  92.     ------------------
  93. if ((hpos>Xpos and hpos<Xpos+50) and (vpos>Ypos and vpos<Ypos+100))then
  94.         red<=(others =>'1');
  95.         green<=(others =>'0');
  96.         blue<=(others =>'0');
  97. end if;
  98.  
  99.      ------------------
  100.     --    Block #2  --
  101.     ------------------
  102.  
  103. if ((hpos>Xpos+100 and hpos<Xpos+150) and (vpos>Ypos+100 and vpos<Ypos+150))then
  104.         red<=(others =>'0');
  105.         green<=(others =>'1');
  106.         blue<=(others =>'0');
  107. end if;
  108.  
  109.      ------------------
  110.     --    Block #3  --
  111.     ------------------
  112.  
  113. if ((hpos>Xpos and hpos<Xpos+50) and (vpos>Ypos and vpos<Ypos+100))then
  114.         red<=(others =>'0');
  115.         green<=(others =>'0');
  116.         blue<=(others =>'1');
  117. end if;
  118.  
  119.      ------------------
  120.     --    Block #4  --
  121.     ------------------
  122.  
  123. if ((hpos>Xpos+100 and hpos<Xpos+150) and (vpos>Ypos+100 and vpos<Ypos+150))then
  124.         red<=(others =>'0');
  125.         green<=(others =>'1');
  126.         blue<=(others =>'1');
  127. end if;
  128.    
  129. end if;
  130. end process;
  131.    
  132.    
  133.  
  134. end main;
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