`timescale 1ns/1ps

module DZ_test;

logic clk, sclr;
reg [2:0] q;

initial
begin
    clk=0;
    forever #10 clk = ~clk;
end

initial
begin
    sclr = 1;
    #30 sclr = 0;
    #100 $stop;

end

DZ uut_inst(clk, sclr, q);

endmodule