library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity alarm is port (
    clk: IN std_logic;
    le : OUT std_logic;
    a: IN std_logic_vector(3 downto 0);
    b: IN std_logic_vector(3 downto 0);
    x: OUT std_logic_vector(1 downto 0));
end alarm;

architecture arch_alarm of alarm is
    type states is (state0, state1, state2, state3 );
    signal stado_pres, stado_fut: states;
begin

p_estados: process(stado_pres,a,b) begin
    case stado_pres is
                when state0 =>
                    x <= "00";
                    le <= '0';
                    if a = NOT(b) then
                        stado_fut <= state1;
                    else
                        stado_fut <= state0;
                    end if;
                when state1 =>
                    x <= "01";
                    if a = NOT(b) then
                        stado_fut <= state2;
                    else
                        stado_fut <= state0;
                    end if;
                when state2 =>
                    x <= "10";
                    if a = NOT(b) then
                        stado_fut <= state3;
                    else
                        stado_fut <= state0;
                    end if;
                when state3 =>
                    x <= "11";
                    if a = NOT(b) then
                        le <= '1';
                    end if;
                    stado_fut <= state0;
            end case;
    end process p_estados;

    p_reloj: process(clk) begin
        if(clk'event and clk= '1') then
            stado_pres <= stado_fut;
        end if;
    end process p_reloj;
end arch_alarm;