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By: a guest on Feb 2nd, 2012  |  syntax: VeriLog  |  size: 0.53 KB  |  hits: 144  |  expires: Never
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  1. module 42adder (a,b,c,d,cin, s,c1,co);
  2. input a,b,c,d,cin;
  3. output s,c1,co;
  4.  
  5. <guts go here>
  6.  
  7. endmodule
  8.  
  9. // module next level up
  10. module nextmoduleup(a,b,c,d,out);
  11. input a,b,c,d,out;
  12. output [2:0] out;
  13.  
  14. wire sparewire = 1'b0;
  15.  
  16. // module type, then name
  17. 42adder myAdder (a,b,c,d,sparewire , out[0], out[1], out[2]);
  18.  
  19. // same connections, different instance, connect by port names
  20. 42adder myConnectbyName(
  21.   .a(a),
  22.   .b(b),
  23.   .c(c),
  24.   .d(d),
  25.   .cin(sparewire),
  26.   .co(out[2]),
  27.   .c1(out[1]),
  28.   .s(out[0])
  29. );
  30.  
  31. endmodule