
Untitled
By: a guest on
Feb 2nd, 2012 | syntax:
VeriLog | size: 0.53 KB | hits: 144 | expires: Never
module 42adder (a,b,c,d,cin, s,c1,co);
input a,b,c,d,cin;
output s,c1,co;
<guts go here>
endmodule
// module next level up
module nextmoduleup(a,b,c,d,out);
input a,b,c,d,out;
output [2:0] out;
wire sparewire = 1'b0;
// module type, then name
42adder myAdder (a,b,c,d,sparewire , out[0], out[1], out[2]);
// same connections, different instance, connect by port names
42adder myConnectbyName(
.a(a),
.b(b),
.c(c),
.d(d),
.cin(sparewire),
.co(out[2]),
.c1(out[1]),
.s(out[0])
);
endmodule