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Jul 31st, 2015
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  1. //(ldm,stm){condition}{mode} rn{!},{r...}
  2. //cccc 100p uswl nnnn llll llll llll llll
  3. //c = condition
  4. //p = pre (0 = post-indexed addressing)
  5. //u = up (add/sub offset to base)
  6. //s = spsr copy -or- usr register copy
  7. //w = writeback
  8. //l = load (0 = save)
  9. //n = rn
  10. //l = register list
  11. auto ARM::arm_op_move_multiple() {
  12. uint1 pre = instruction() >> 24;
  13. uint1 up = instruction() >> 23;
  14. uint1 s = instruction() >> 22;
  15. uint1 writeback = instruction() >> 21;
  16. uint1 l = instruction() >> 20;
  17. uint4 n = instruction() >> 16;
  18. uint16 list = instruction();
  19.  
  20. uint32 rn = r(n);
  21. if(pre == 0 && up == 1) rn = rn + 0; //IA
  22. if(pre == 1 && up == 1) rn = rn + 4; //IB
  23. if(pre == 1 && up == 0) rn = rn - bit::count(list) * 4 + 0; //DB
  24. if(pre == 0 && up == 0) rn = rn - bit::count(list) * 4 + 4; //DA
  25.  
  26. Processor::Mode pmode = mode();
  27. bool usr = false;
  28. if(s && l == 1 && (list & 0x8000) == 0) usr = true;
  29. if(s && l == 0) usr = true;
  30.  
  31. if(usr) processor.setMode(Processor::Mode::USR);
  32.  
  33. unsigned sequential = Nonsequential;
  34. for(unsigned m = 0; m < 16; m++) {
  35. if(list & 1 << m) {
  36. if(l == 1) r(m) = read(Word | sequential, rn);
  37. if(l == 0) write(Word | sequential, rn, r(m));
  38. rn += 4;
  39. sequential = Sequential;
  40. }
  41. }
  42.  
  43. if(usr) processor.setMode(pmode);
  44.  
  45. if(l == 1) {
  46. idle();
  47. if(s && (list & 0x8000)) {
  48. if(mode() != Processor::Mode::USR && mode() != Processor::Mode::SYS) {
  49. cpsr() = spsr();
  50. processor.setMode((Processor::Mode)cpsr().m);
  51. }
  52. }
  53. } else {
  54. pipeline.nonsequential = true;
  55. }
  56.  
  57. if(writeback) {
  58. if(up == 1) r(n) = r(n) + bit::count(list) * 4; //IA, IB
  59. if(up == 0) r(n) = r(n) - bit::count(list) * 4; //DA, DB
  60. }
  61. }
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