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- //(ldm,stm){condition}{mode} rn{!},{r...}
- //cccc 100p uswl nnnn llll llll llll llll
- //c = condition
- //p = pre (0 = post-indexed addressing)
- //u = up (add/sub offset to base)
- //s = spsr copy -or- usr register copy
- //w = writeback
- //l = load (0 = save)
- //n = rn
- //l = register list
- auto ARM::arm_op_move_multiple() {
- uint1 pre = instruction() >> 24;
- uint1 up = instruction() >> 23;
- uint1 s = instruction() >> 22;
- uint1 writeback = instruction() >> 21;
- uint1 l = instruction() >> 20;
- uint4 n = instruction() >> 16;
- uint16 list = instruction();
- uint32 rn = r(n);
- if(pre == 0 && up == 1) rn = rn + 0; //IA
- if(pre == 1 && up == 1) rn = rn + 4; //IB
- if(pre == 1 && up == 0) rn = rn - bit::count(list) * 4 + 0; //DB
- if(pre == 0 && up == 0) rn = rn - bit::count(list) * 4 + 4; //DA
- Processor::Mode pmode = mode();
- bool usr = false;
- if(s && l == 1 && (list & 0x8000) == 0) usr = true;
- if(s && l == 0) usr = true;
- if(usr) processor.setMode(Processor::Mode::USR);
- unsigned sequential = Nonsequential;
- for(unsigned m = 0; m < 16; m++) {
- if(list & 1 << m) {
- if(l == 1) r(m) = read(Word | sequential, rn);
- if(l == 0) write(Word | sequential, rn, r(m));
- rn += 4;
- sequential = Sequential;
- }
- }
- if(usr) processor.setMode(pmode);
- if(l == 1) {
- idle();
- if(s && (list & 0x8000)) {
- if(mode() != Processor::Mode::USR && mode() != Processor::Mode::SYS) {
- cpsr() = spsr();
- processor.setMode((Processor::Mode)cpsr().m);
- }
- }
- } else {
- pipeline.nonsequential = true;
- }
- if(writeback) {
- if(up == 1) r(n) = r(n) + bit::count(list) * 4; //IA, IB
- if(up == 0) r(n) = r(n) - bit::count(list) * 4; //DA, DB
- }
- }
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